Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-17
2002-12-17
Decady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S341000
Reexamination Certificate
active
06496954
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Viterbi decoder and a Viterbi decoding method which are to be used for decoding a received signal, and more particularly to a Viterbi decoder and a Viterbi decoding method which are suitable for an ADSL (Asymmetric Digital Subscriber Line) modem.
2. Description of the Related Art
In recent years, the introduction of an ADSL (Asymmetric Digital Subscriber Line) has been examined in the field of a wide-band multimedia telecommunication. The ADSL is a network in which an up transmission speed from a individual home to a telephone station is set to 16 kbps to 1.3 Mbps, for example, and a down transmission speed from the telephone station to the individual home is set to 1.5 Mbps to 12 Mbps, for example, and the transmission speeds are thus asymmetrical.
In such an ADSL, the specification of a transmitter is standardized.
FIG. 1
is a block diagram showing an encoder provided on a transmitter in the ADSL.
The encoder provided on the transmitter is provided with a Trellis encoding circuit
27
for adding an error correction code to de-map data before mapping. Moreover, the encoder is provided with a tone ordering buffer memory
23
for storing data output from the Trellis encoding circuit
27
and rearranging, in the order of a frequency, carriers arranged in the order of an allocated bit number to be described below. Furthermore, the encoder is provided with a tone ordering table
25
in which tone ordering table data to be used for the above-mentioned rearrangement is stored and with a read/write controller
24
for controlling the storage and read of the data in the tone ordering buffer memory
23
based on the tone ordering table data. There is provided a transmitting bit allocation table
22
in which a bit allocation number N (≦15) of an i-th carrier to be transmitted is stored, and a mapping circuit
21
for mapping the data output from the tone ordering buffer memory
23
for each carrier based on a constellation map. A transmitting constellation X coordinate and a transmitting constellation Y coordinate are output for each carrier from the mapping circuit
21
. Thus, the mapping data are encoded into the transmitting constellation X coordinate and the transmitting constellation Y coordinate.
FIG. 2
is a diagram typically showing a constellation map obtained when the bit allocation number is 4 bits. A sent signal is allocated to a point having odd-numbered X and Y coordinates. This allocation is similarly carried out for any bit allocation number. If the bit allocation number is 4 bits, a constellation coordinate of (1, 3) is obtained when data of “0001” is transmitted and a constellation coordinate of (−3, −1) is obtained when data of “1101” is transmitted.
As described, the maximum number of the bit allocation number is 15 bits. Therefore, the maximum bit number of the transmitting constellation X coordinate and the transmitting constellation Y coordinate is 9 bits. More specifically, in the case where the number of dots as black circles is extended to 15×15 as shown in
FIG. 2
, the maximum value of the X and Y coordinates is 9 bits in a binary number.
Then, the encoded data are related to 256 carriers provided in a frequency band between 4 kHz to 1 MHz for one symbol. The above-mentioned bit allocation number is a bit number to be allocated to each carrier.
Next, the transmitting constellation X coordinate and the transmitting constellation Y coordinate are subjected to inverse fast Fourier transform (IFFT) and are transmitted to a receiver.
Under the present circumstances, however, the specification of the transmitter is standardized as described above, while the structure of the Viterbi decoder to be used corresponding to the encoder and provided on the receiver is not standardized. For this reason, a Viterbi decoder capable of being used for the receiver and carrying out the decoding operation with high precision has been required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a Viterbi decoder and a Viterbi decoding method which can be used for an ADSL modem and can preferably simplify the structure of a circuit.
According to one aspect of the present invention, a Viterbi decoder comprises a coordinate data separating system which inputs coordinate data, and which outputs high order coordinate data and low order coordinate data. The coordinate data have an integer part of n bits and a decimal part of m bits which indicate a receiving constellation coordinate. The high order coordinate data have high order n−1 bits of the coordinate data. The low order coordinate data have low order m+1 bits of the coordinate data. The Viterbi decoder comprises also a de-mapping system which converts the high order coordinate data into a predetermined bit string, and a Viterbi pre-processing system which inputs the low order coordinate data and the bit string, and which outputs correcting data, post-processing data and the bit string. The correcting data have low order m bits of the bit string and the low order coordinate data. The post-processing data have high order 1 bit of the low order coordinate data. The Viterbi decoder comprises also a Viterbi decoding system which inputs the correcting data, and which outputs a corrected low order bit string, and a Viterbi post-processing system which inputs the corrected low order bit string, the post-processing data and the bit string, and which outputs a corrected bit string. The corrected low order bit string is obtained by correcting a low order bit string having low order 2 bits of the bit string.
According to the present invention, a substantially reverse process to the process in the transmitter is carried out. Therefore, the decoding operation can be performed with high precision.
According to another aspect of the present invention, a Viterbi decoder comprises a Viterbi pre-processing system which inputs coordinate data, and which outputs high order coordinate data and low order coordinate data. The coordinate data have an integer part of n bits and a decimal part of m bits which indicate a receiving constellation coordinate. The high order coordinate data have high order n−1 bits of the coordinate data, and the low order coordinate data having low order m+1 bits of the coordinate data. The Viterbi decoder comprises also a Viterbi decoding system which inputs the low order coordinate data, and which outputs post-processing data. The post-processing data is obtained by error-correcting high order 1 bit of the low order coordinate data. The Viterbi decoder comprises also a Viterbi post-processing system which inputs the high order coordinate data and the post-processing data, and which outputs error-corrected coordinate data, and a de-mapping system which converts the error-corrected coordinate data into a predetermined bit string.
According to the present invention, the error correction is carried out prior to the conversion into the bit string. Therefore, it is possible to carry out the decoding operation with high precision and to simplify the structure of the means for converting the bit string.
According to another aspect of the present invention, A Viterbi decoding method comprises the steps of: separating coordinate data into high order coordinate data and low order coordinate data, the coordinate data having an integer part of n bits and a decimal part of m bits which indicate a receiving constellation coordinate, the high order coordinate data having high order n−1 bits of the coordinate data, and the low order coordinate data having low order m+1 bits of the coordinate data; converting the high order coordinate data into a predetermined bit string; generating correcting data and post-processing data from the low order coordinate data and the bit string, the correcting data having low order m bits of the bit string and the low order coordinate data, and the post-processing data having high order 1 bit of the low order coordinate data; generating a corr
Chase Shelly A
De'cady Albert
Whitham Curtis & Christofferson, P.C.
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