Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-01-05
2009-08-18
Kim, Matt (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S135000, C711S138000, C711S144000, C711S156000
Reexamination Certificate
active
07577791
ABSTRACT:
A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting addressing mode information within an instruction such that if present, data may be obtained from the load buffers, rather than accessing a cache memory or other memory device within the computer system.
REFERENCES:
patent: 6535962 (2003-03-01), Mayfield et al.
Jim Handy, The Cache Memory Book, 1998, Academic Press, Second Edition, pp. 16 and 47-48.
David A. Patterson and John L. Hennessy, Computer Architecture A Quantitative Approach, 1996, Second Edition, p. 75.
Fernando John
Kolagotia Ravi
Peri Ramesh
Gu Shawn X
Intel Corporation
Kim Matt
Trop Pruner & Hu P.C.
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