Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status
Reexamination Certificate
2007-10-09
2007-10-09
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Processor status
C710S260000, C718S102000, C718S105000
Reexamination Certificate
active
10422513
ABSTRACT:
A method, system, and article of manufacture for processing virtual interrupts in a logically partitioned system are provided. An intelligent virtual global interrupt queue (virtual GIQ) that may be associated with a plurality of virtual processors running in a logical partition may be utilized. Upon receiving a virtual interrupt, the virtual GIQ may examine the operating states of the associated virtual processors. In an effort to ensure the virtual interrupt is processed as quickly as possible, the virtual GIQ may present the virtual interrupt to one of the associated virtual processors determined to be in an operating state best suited for processing the virtual interrupt.
REFERENCES:
patent: 4135240 (1979-01-01), Ritchie
patent: 4400769 (1983-08-01), Kaneda et al.
patent: 4742447 (1988-05-01), Duvall et al.
patent: 4843541 (1989-06-01), Bean et al.
patent: 4885681 (1989-12-01), Umeno et al.
patent: 4959781 (1990-09-01), Rubinstein et al.
patent: 5095427 (1992-03-01), Tanaka et al.
patent: 5187802 (1993-02-01), Inoue et al.
patent: 5222215 (1993-06-01), Chou et al.
patent: 5325525 (1994-06-01), Shan et al.
patent: 5325526 (1994-06-01), Cameron et al.
patent: 5357632 (1994-10-01), Pian et al.
patent: 5361375 (1994-11-01), Ogi
patent: 5404563 (1995-04-01), Green et al.
patent: 5481747 (1996-01-01), Kametani
patent: 5504670 (1996-04-01), Barth et al.
patent: 5535321 (1996-07-01), Massaro et al.
patent: 5574914 (1996-11-01), Hancock et al.
patent: 5659786 (1997-08-01), George et al.
patent: 5692193 (1997-11-01), Jagannathan et al.
patent: 5694606 (1997-12-01), Pletcher et al.
patent: 5872963 (1999-02-01), Bitar et al.
patent: 5898855 (1999-04-01), Onodera et al.
patent: 5978830 (1999-11-01), Nakaya et al.
patent: 6078970 (2000-06-01), Nordstrom et al.
patent: 6105050 (2000-08-01), Govindaraju et al.
patent: 6195676 (2001-02-01), Spix et al.
patent: 6199093 (2001-03-01), Yokoya
patent: 6247109 (2001-06-01), Kleinsorge et al.
patent: 6269391 (2001-07-01), Gillespie
patent: 6279046 (2001-08-01), Armstrong et al.
patent: 6381742 (2002-04-01), Forbes et al.
patent: 6418460 (2002-07-01), Bitar et al.
patent: 6487654 (2002-11-01), Dowling
patent: 6542926 (2003-04-01), Zalewski et al.
patent: 6587938 (2003-07-01), Eilert et al.
patent: 6598069 (2003-07-01), Rooney et al.
patent: 6615303 (2003-09-01), Endo et al.
patent: 6625638 (2003-09-01), Kubala et al.
patent: 6647508 (2003-11-01), Zalewski et al.
patent: 6711605 (2004-03-01), Sekiguchi et al.
patent: 6760783 (2004-07-01), Berry
patent: 6779065 (2004-08-01), Murty et al.
patent: 2001/0014905 (2001-08-01), Onodera
patent: 2002/0056076 (2002-05-01), van der Made
patent: 2003/0014466 (2003-01-01), Berger et al.
patent: 2003/0046464 (2003-03-01), Murty et al.
patent: 2003/0093655 (2003-05-01), Gosior et al.
patent: 2003/0101440 (2003-05-01), Hardin et al.
patent: 01-093830 (1989-04-01), None
patent: 02-090331 (1990-03-01), None
patent: 07-160656 (1995-06-01), None
patent: 2001188685 (2001-07-01), None
Kaneda et al. A Virtual Machine Monitor for Providing a Single System Image. IPDPS Submission. 2006.
Scott et al. Multi-Model Parallel Programming in Psyche. Proceedings of the second ACM SIGPLAN symposium on Principles and practice of parallel programming. 1990.
Bakshi et al., “Partitioning and Pieplining for Performance-Constrained Hardware/Software Systems,” 1999 IEEE, pp. 419-432.
Ayachi et al., “A Hierarchical Processor Scheduling Policy for Multiprocessor Systems,” 1996 IEEE, pp. 100-109.
Marisa Gil et al., “The Enhancement of a User-level Thread Package Scheduling on Multiprocessors,” Sep. 1994, Euromicro Workshop on Parallel and Distributed Processing, pp. 228-236.
IBM AS/400e Logical Partitions: Learning About. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzajx.pdf.
IBM AS/400e Logical Partitions: Planning for. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzait.pdf.
IBM AS/400e Logical Partitions: Creating. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj7.pdf.
IBM AS/400e Logical Partitions: Managing. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj6.pdf.
IBM AS/400e Logical Partitions: Troubleshooting. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj8.pdf.
IBM Corporation, S/390 Processor Resource/Systems Manager Planning Guide (IBM Pub. No. GA22-7236-04, 5thEdition, Mar. 1999).
Menasce, D. et al. “Capacity Planning and Performance Modeling”, ISBN 0-13-035494-5, © 1994.
Leutenegger et al. “A Modeling Study of the TPC-C Benchmark”, Proceedings of the 1993 ACM SIGMOD Int'l Conference on Management of Data, 1993, pp. 22-31.
Levine, C. “Order-of-Magnitude Advantage on TPC-C Through Massive Parallelism”, Proceedings of the 1995 ACM SIGMOD Int'l Conference on Management of Data, 1995, pp. 464-465.
IBM Corporation, “AS/400 Logical Partitions Hardware Planning Guide”, © 1999.
Schimunek, G. et al. “Slicing the AS/400 With Logical Partitioning: A How to Guide”, Aug. 1999.
IBM Corporation, “LPAR Configuration and Management”, First Edition, © Apr. 2002.
David L. Black, “Scheduling Support for Concurrency and Parallelism in the Mach Operating System,” Computer, IEEE Computer Society, vol. 23, No. 5, May 1, 1990, pp. 35-43.
T. L. Borden et al., “Multiple Operating Systems on One Processor Complex,” IBM Systems Journal, vol. 28, No. 1, 1989, pp. 104-122.
Shigekazu Inohara et al., “A Thread Facility Based on User/Kernel Cooperation in the XERO Operating System,” Computer Software and Applications Conference, 1991, Sep. 11, 1991, pp. 398-405.
U.S. Appl. No. 09/838,057, “Method and Apparatus for Allocating Processor Resources in a Logically Partitioned Computer System,” Armstrong et al., filed Apr. 19, 2001.
U.S. Appl. No. 10/403,158, “Apparatus and Method for Virtualizing Interrupts in a Logically Partitioned Computer System,” Armstrong et al., filed Mar. 31, 2003.
Armstrong William Joseph
Larson David Anthony
Nayar Naresh
International Business Machines - Corporation
Patterson & Sheridan LLP
Rinehart Mark H.
Spittle Matthew
LandOfFree
Virtualization of a global interrupt queue does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Virtualization of a global interrupt queue, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtualization of a global interrupt queue will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3885486