Virtual two-port memory structure with fast write-thru operation

Static information storage and retrieval – Addressing – Multiple port access

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36518907, 36523008, 36523001, G11C 800

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active

057611475

ABSTRACT:
A virtual two-port memory structure with fast write-thru operation is proposed. The virtual two-port memory structure employs a single-port memory cell (200). Means for comparing (260) compare a read address AR with a write address AW and means (270) for writing data from the data input terminal (250) into the cell (200) are bypassing said data to the data output terminal (280) as well, such that a write-thru operation is enabled if the read address AR matches the write address AW. The data just written into the cell are immediately available as read data within the same cycle. The multiplex unit used in prior art solutions is no longer necessary, the delay caused by this device is omitted and the advantages of the virtual two-port cell requiring less chip space are maintained.

REFERENCES:
patent: 5430685 (1995-07-01), Nakada
patent: 5473574 (1995-12-01), Clemen et al.
patent: 5657291 (1997-08-01), Podlesny et al.
"Dense multi-port cell scheme", IBM TDB, vol. 30, No. 7, Dec. 1987, pp. 320-321.
"Reconfigurable single/dual port RAM system", IBM TDB, vol. 29, No. 4, Sep. 1986, pp. 1881-1882.

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