Virtual to logical to physical address translation for distribut

Details Virtual to logical to physical address translation for distribut Virtual to logical to physical address translation for distribut

1993-12-13

1998-07-21

Moore, David K.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, 711205, 711206, 711207, 711208, G06F 1210, G06F 1206

Patent

active

057847061

ABSTRACT:
Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

REFERENCES:
patent: 4523273 (1985-06-01), Adams et al.
patent: 4654791 (1987-03-01), Ushiro
patent: 4985829 (1991-01-01), Thatte et al.
patent: 5117350 (1992-05-01), Parrish et al.
patent: 5151969 (1992-09-01), Petsche
patent: 5165028 (1992-11-01), Zulican
patent: 5247629 (1993-09-01), Casamatta et al.
patent: 5392416 (1995-02-01), Toshio et al.
patent: 5404485 (1995-04-01), Ban
patent: 5434995 (1995-07-01), Oberlin et al.
Information Processing 89, Proceeding of the IFIP 11th World Computer Congress, 28 Aug. 1989 San Francisco, US, pp. 995-1000, XP 000079023, Murakami et al., "The Kyushu University Reconfigurable Parallel Processor-Design Philosophy and Architecture", see abstract, see p. 999, right col., line 7-p. 1000, left col., line 8; Figure 6.
Distributed Computing, vol. 1, No. 4, Oct. 1986, Berlin DE, pp. 187-196, XP 000054632 Dally et al., "The torus routing chip", see p. 190, left col., line 1-p. 191, right col., line 22.
Patent Abstracts of Japan, vol. 017, No. 602 (P-1638), Nov. 5, 1993, and JP,A,05 181751 (Fujitsu Ltd), Jul. 1993.
Tom MacDonald, et a. "Addressing in Cray Research's MPP Fortran," Proceedings, Third Workshop on Compilers for Parallel Computers, ACPC/TR, Jul., 1992.
Erik P. DeBenedictis, et al. "Extending Unix for Scalable Computing," Computer, vol. 26, No. 11, pp. 43-53, Nov., 1993.
David Loveman, "Element Array Assignment-the Forall Statement," Proceedings, Third Workshop on Compilers for Parallel Computers, ACPC/TR, Jul., 1992.
Min-You, Wu, et al., "DO and Forall: Temporal and Spacial Control Structures," Proceedings, Third Workshop on Compilers for Parallel Computers, ACPC/TR, Jul., 1992.
Philip J. Hatcher, et al., "Compiling Data-Parallel Programs for MIMD Architectures," Proceedings, Third Workshop on Compilers for Parralel Computers, ACPC/TR, Jul., 1992.
Barbara Chapman, et al., "Programming in Vienna Fortran," Procceedings, Third Workshop on Compilers for Parallel Computers, ACPC/TR, Jul., 1992.

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