Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-12-19
2003-11-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S194000, C365S236000, C365S240000
Reexamination Certificate
active
06646943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a virtual static random access memory device and a driving method therefor, and in particular to an improved virtual static random access memory device which uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor.
2. Description of the Background Art
In general, a static random access memory (hereinafter, referred to as “SRAM”) has been widely used in the field of small or middle-sized computers due to its ability to provide high speed operation, in spite of inferior integration to the DRAM. An SRAM cell includes a flip flop circuit consisting of two access transistors, two drive transistors and two load elements. Here, information is stored as accumulated charges in a voltage difference between the I/O terminals of the flip flop circuit, which define a node of the cell. The charges are always applied from a power supply source Vcc through a PMOS transistor or a load resistor. Accordingly, the SRAM does not require a refresh function as in the DRAM.
The SRAM cell may employ a depletion NMOS transistor as the load element. However, use of the depletion NMOS transistors has been rare due to the high power consumption. Recently, the SRAM cell has used high resistance polysilicon as the load element because it provides for low power consumption and simplified fabrication. According to an increased memory capacity and a high resistance value, there has been suggested a full CMOS SRAM cell using a bulk type PMOS transistor as the load element to obtain a low operation voltage. Advantageously, the full CMOS SRAM cell consumes less power in a standby mode and has high immunity to &agr;-particles.
FIG. 1
is a circuit diagram illustrating a memory cell of a conventional SRAM device using a PMOS transistor as a load element. Referring to
FIG. 1
, each of the SRAM cells includes: a pair of inverters connected in parallel between a power supply terminal Vcc and a ground terminal Vss; and first and second access transistors N
3
, N
4
having their source regions (or drain regions) connected to output terminal of the inverters, respectively. Here, the first and second access transistors N
3
, N
4
have their drain regions (or source regions) connected to a first bit line BL and a second bit line /BL, respectively. In addition, the first inverter includes a first load transistor P
1
consisting of a PMOS transistor and a first drive transistor N
1
consisting of an NMOS transistor, and the second inverter includes a second load transistor P
2
consisting of a PMOS transistor and a second drive transistor N
2
consisting of an NMOS transistor. The first and second access transistors N
3
, N
4
consist of NMOS transistors having their gate electrodes connected to a word line WL. In order to compose one latch circuit, an input terminal of the first inverter is connected to an output terminal of the second inverter, and an input terminal of the second inverter is connected to an output terminal of the first inverter.
On the other hand, the size of an SRAM memory cell of 16M or higher integration should be reduced for high integration. However, in the case of the full CMOS SRAM cell, six transistors, namely a pair of drive transistors, a pair of access transistors and a pair of load transistors are aligned on a plane, which results in poor integration. Therefore, the SRAM cell has not been popularly applied to VLSI chips in spite of excellent operational characteristics. Accordingly, high integration can be achieved in SRAM cells by introducing a DRAM cell composing one cell with one transistor and one capacitor.
FIG. 2
is a circuit diagram illustrating a general DRAM cell. As depicted in
FIG. 2
, the memory cell of the DRAM includes an NMOS transistor
1
and a capacitor
2
for accumulating data as charges. Here, the NMOS transistor
1
has its source region (or drain region) connected to a bit line BL, and its gate region connected to a word line WL. The capacitor
2
is connected between the source region (or drain region) of the NMOS transistor
1
and the ground terminal, Vss.
When the SRAM is embodied by using the DRAM cell including one transistor and one capacitor, the SRAM is highly integrated, but has other problems. That is, the DRAM cell requires a refresh operation that is different from that of the SRAM. Accordingly, in order to embody the SRAM by using the DRAM cell, the refresh operation needs to be internally processed. In addition, the SRAM and the DRAM have different operation rules on a data sheet.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of the present invention to provide a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell.
Another object of the present invention is to provide a method for driving a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell.
In order to achieve the above-described objects of the present invention, there is provided a virtual static random access memory device including: a memory cell array having a memory cell requiring a refresh operation; an I/O driving unit for inputting/outputting data to/from the memory cell array; a register for storing data in the memory device; a refresh controller for controlling the refresh operation on the memory cell array; and a state controller for enabling the register to store the input data, the refresh controller to perform the refresh operation on the memory cell array, and the I/O driving unit to perform a recording operation on the memory cell array by using the input data stored in the register, when a recording operation is performed on the memory cell array for a longer time than a refresh period and a predetermined time elapses from the recording operation. Preferably, an input buffer for externally receiving input data and transmitting the data to the remaining elements of device is also included.
The state controller includes elements for sequentially performing a precharge operation and a refresh operation, when a refresh request is inputted and control signals for controlling a valid data are not varied for a predetermined time. The state controller further includes elements for performing a succeeding recording operation by using the data stored in the register, when a previous recording cycle is valid after the refresh operation and is not sufficiently long to finish the recording operation. Preferably, an address comparing unit for comparing an address stored in the register with a currently-inputted address is included, wherein, when the address comparing unit judges that the two addresses are identical in the read operation on the memory cell array, the state controller outputs the data stored in the register. Preferably, there is also included an address comparing unit for comparing an address stored in the register with a currently-inputted address, wherein, when the address comparing unit judges that the two addresses are identical in the recording operation on the memory cell array, the state controller records the currently-inputted data on the memory cell array. Preferably, there is also included an address comparing unit for comparing an address stored in the register with a currently-inputted address, wherein, when the address comparing unit judges that the two addresses are identical in the recording operation on the memory cell array, the state controller replaces the currently-inputted data by the data stored in the register, and records the data on the memory cell array. Preferably, there is further included an address comparing unit for comparing an address stored in the register with a currently-inputted address, wherein, when the address comparing unit judges that the two addresses are identical in the recording operation on the memory cell array and when a byte control signal is inputted, the state controller replaces the data stored in the register by the currently-inputted data in byte units, and reco
Elms Richard
Hynix / Semiconductor Inc.
Ladas & Parry
Le Toan
LandOfFree
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