Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-04-17
2007-04-17
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S118000
Reexamination Certificate
active
10860523
ABSTRACT:
A physical address extension feature maps multiple virtual memory spaces to an extended physical memory. A virtual space manager dynamically allocates pages of the physical memory to respective virtual spaces. The virtual space manager responds to a request from an application for allocation of a page of physical memory by returning a cookie indicating the allocated page. The virtual space manager responds to a request including the cookie by switching virtual address translation to the virtual memory space including the indicated page. The cookie is used to access a cookie cache of state information on the last page of virtual memory having been mapped into physical memory. For example, segments of the page store block map entries for snapshot copies, and the cookie cache caches the last-accessed values of the block numbers and their location within the page.
REFERENCES:
patent: 4445174 (1984-04-01), Fletcher
patent: 4691280 (1987-09-01), Bennett
patent: 5606683 (1997-02-01), Riordan
patent: 5737605 (1998-04-01), Cunningham et al.
patent: 5873120 (1999-02-01), Harvey et al.
patent: 5893140 (1999-04-01), Vahalia et al.
patent: 6003123 (1999-12-01), Carter et al.
patent: 6081802 (2000-06-01), Atherton et al.
patent: 6112286 (2000-08-01), Schimmel et al.
patent: 6182089 (2001-01-01), Ganapathy et al.
patent: 6185575 (2001-02-01), Orcutt
patent: 6240501 (2001-05-01), Hagersten
patent: 6314501 (2001-11-01), Gulick et al.
patent: 6324581 (2001-11-01), Xu et al.
patent: 6381682 (2002-04-01), Noel et al.
patent: 6430667 (2002-08-01), Loen
patent: 6430668 (2002-08-01), Belgard
patent: 6434681 (2002-08-01), Armangau
patent: 6442682 (2002-08-01), Pothapragada et al.
patent: 6477612 (2002-11-01), Wang
patent: 6549992 (2003-04-01), Armangau et al.
patent: 6594735 (2003-07-01), Baker et al.
patent: 6604182 (2003-08-01), Sexton et al.
patent: 6618792 (2003-09-01), Perrin et al.
patent: 6622229 (2003-09-01), Morgenstern et al.
patent: 6799173 (2004-09-01), Czajkowski et al.
patent: 6981125 (2005-12-01), Emmes
patent: 7010655 (2006-03-01), Harmer et al.
patent: 2003/0018691 (2003-01-01), Bono
patent: 2004/0030727 (2004-02-01), Armangau et al.
patent: 2004/0030846 (2004-02-01), Armangau et al.
patent: 2004/0030951 (2004-02-01), Armangau et al.
patent: 2004/0128542 (2004-07-01), Blakley et al.
patent: 2005/0015354 (2005-01-01), Grubbs et al.
patent: 2005/0216695 (2005-09-01), Bono
patent: 2260429 (1993-04-01), None
patent: WO 9714084 (1997-04-01), None
EMC Celerra SE5 File Server, EMC Corporation, Hopkinton, MA, 2002, 2 pages.
“Celerra File Server in the E-Infostructure,” EMC Corporation, Hopkinton, MA, 2000, 9 pages.
“Celerra File Server Architecture for High Availability,” EMC Corporation, Hopkinton, MA, 1999, pp. 1-7.
“MultiProcessor Specification Version 1.4,” May 1997, Intel Corporation, Mt. Prospect, IL, 1993-1997, 1-1 to 5-8, A-1 to E-6.
Helen S. Raizen and Stephen C. Schwarm, “Building a Semi-Loosely Coupled Multiprocessor System Based on Network Process Extension,” Prime Computer, Inc., Framingham, MA, Pre-Publication Copy, Jan. 29, 1991, pp. 1-17.
Morioka et al., “Design and Evaluation of the High Performance Multi-Processor Server,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society Press, Los Alamitos, CA 1994, pp. 66-69.
“Intel Xeon Processor: Unparalleled Value and Flexibility for Small and Medium Business Server Applications,” Intel Corporation, Santa Clara, CA, 2002, 4 pages.
“Intel Server Board SE7500WV2;” Intel Corporation, Santa Clara, CA, 2002, 6 pages.
“Building Cutting-Edge Server Applications: Intel Xeon Processor Family Features the Intel NetBurst Microarchitecture with Hyper-Threading Technology;” White Paper, Intel Corporation, Santa Clara, CA, 2002, 10 pages.
Levy & Eckhouse, Jr.,Computer Programming and Architecture—The VAX-11, Digital Equipment Corporation, Bedford, Mass., 1980, pp. 247-253, 356-360.
Intel 80386 Reference Programmer's Manual, Table of contents (4 pages),Chapter 2.1 Memory Organization and Segmentation (2 pages), Chapter 5 Memory Management (2 pages), Chapter 5.1 Segment Translation (6 pages), Chapter 5.2 Page Translation (4 pages), Chapter 5.3 Combining Segment and Page Translation (3 pages), , http://www7.informatik.uni-erlangen.de, Friederich-Alexander-Universitat, Erlangen-Nurnberg, Germany.
Addendum—Intel Architecture Software Developer's Manual, vol. 3: System Programming Guide, Intel Corp., Santa Clara, CA 1997, pp. 3-1 to 3-4 and 9-1 to 9-8.
The 1A-32 Intel® Architecuter Software Developer's Manual, vol. 3, System Programming Guide, Intel Corp., Santa Clara, CA, 2004, Table of Contents and pp. 3-1 to 3-38.
“PAE36 and Linux Virtual Memory System—The Need for PAE32,” www.prism.gatech.edu, Georgia Institute of Technology, Atlanta, Georgia, printed Dec. 5, 2003, 4 pages.
“Windows—Operating System and PAE Support,” www.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 6 pages.
“Physical Address Extension X86 Overview,” www.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 1 page.
“Intel Physical Address Extensions (PAE) in Windows 2000,” http://support.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 1 page.
“PAE Design,” www.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 3 pages.
“PAE Memory and Windows,” www.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 10 pages.
“How to Configure the Paged Address Pool and System Page Table Entry Memory Areas,” http://support.microsoft.com, Microsoft Corp., Bellevue, WA, 2003, 4 pages.
“Scaling Out Verses Scaling Up with Intel Physical Addressing Extensions (PAE),” http://support.microsoft.com, Microsoft Corp., Bellevue, WA, printed Dec. 5, 2003, 1 page.
“Physical Address Extension (PAE)—PAE Memory Support,” www.osr.com, OSR Open Systems Resources, Inc., Amherst, NH, printed Dec. 5, 2003, 6 pages.
IA-32 Intel® Architecture Optimization Reference Manual, Order No. 248966-010, Intel Corporation, 2004, Santa Clara, CA, 2004, pp. 1-28 to 1-34 and 10-1 to 10-44.
“Cookie: Dictionary Entry and Meaning,” Webnox Corp., www.hyperdictionary.com, printed Apr. 6, 2004, one page.
“Malloc—A Memory Allocator,” The Open Group Specifications Issue 6, IEEE Std 1003.1, www.opengroup.org, printed May 28, 2004, 2 pages.
“Memory Management Reference: Memory Management in Win32®,” www.memorymanagement.org, printed May 28, 2004, 1 page.
“Memory Management Reference: Beginner's Guide: Allocation,” www.memorymanagement.org, printed May 28, 2004, 4 pages.
“Memory Management Reference: Frequently Asked Questions,” www.memorymanagement.org, printed May 28, 2004, 10 pages.
Doug Leo, “A Memory Allocator,” Oswego State University of New York, Oswego, NY, www.oswego.edu, printed May 28, 2004, 8 pages.
Ahmed Ishraq Mohammed
Armangau Philippe
DeSouter Marc A.
Glidewell Keith
Auchterlonie Richard C.
Bataille Pierre-Michel
Novak Druce & Quigg LLP
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