Virtual serial data transfer mechanism

Details Virtual serial data transfer mechanism Virtual serial data transfer mechanism

1997-05-07

2000-07-25

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 52, 710 30, 709300, G06F 1516

Patent

active

060946962

ABSTRACT:
A plurality of data devices are interfaced to a microprocessor using a serial data transfer mechanism. The parallel data from the data devices is serialized. The serial data streams are multiplexed via a data multiplexer. An index signal identifies the data device from which the serial data is received/transmit. When a receive buffer is at a predefined level of emptiness, a bit associated with that buffer is asserted. Likewise, when a transmit buffer is at a predefined level of emptiness, a bit within the index register associated with the transmit buffer is asserted. The assertion of a bit within the index register generates an interrupt. A CPU core receives the interrupt signal and reads the index register to determine which buffers need servicing. The CPU core deasserts one bit of the index register, which indicates the CPU core is going to service the buffer associated with that bit. If the bit in the index register is associated with a receive buffer, the deassertion of the bit causes the receive buffer to output receive data to the CPU core. Likewise, if the bit deasserted by the CPU core is associated with the transmit buffer, the deassertion of the bit within the index register causes the transmit buffer to input data from the CPU core.

REFERENCES:
patent: 4228496 (1980-10-01), Katzman et al.
patent: 4663706 (1987-05-01), Allen et al.
patent: 5687396 (1997-11-01), Satoh et al.
patent: 5740468 (1998-04-01), Hirose
patent: 5784649 (1998-07-01), Begur et al.

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