Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1997-11-03
2001-01-23
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S202000
Reexamination Certificate
active
06178482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of processors. More specifically, the present invention relates to the art of instruction execution practiced on processors.
2. Background Information
Prior art approaches to instruction execution practiced by processors can be broadly classified into three approaches based on the manner operand storage is handled. Broadly defined, the three approaches are stack based approach, accumulator based approach and register based approach. Stack, accumulator and registers are different functional forms of temporary storage medium employed in processor datapaths, which in addition to the temporary storage medium, includes arithmetic logic units (ALU) and so forth. Register is characterized by their symbolic designations through register identifiers, i.e. R1, R2 and so forth. The term processor as used herein in the present specification is intended to include micro-controllers (MCU), digital signal processors (DSP), general purpose microprocessors (uP), and the like, whereas the term instruction as used herein is intended to include macro-instructions visible to programmers or compiler writers as well as micro-instructions, micro-operations, or primitive operations and the like that are not visible to programmers and compiler writers.
In the case of the stack based approach, one of the source as well as the destination operand of an instruction are implicitly defined to be located at the top of the stack, whereas, in the case of the accumulator based approach, one of the source as well as the destination operand of an instruction are implicitly defined to be located in the accumulator. Typically, the other source operand is located in a register. In the case of the register set based approach, the source and the destination operands of an instruction are either located in registers or in memory locations. While registers are specified by their identifiers, memory locations, whether cached or not, are specified by either physical or virtual addresses, depending on the manner in which memory is managed.
While the stack based approach enjoys the advantage of providing a simple model for expression evaluation, and short instruction, the approach suffers from at least the disadvantages of forcing all the operands onto the stack, and yet not being able to randomly access the pushed down operands in the stack, resulting in inefficient coding. As to the accumulator approach, while it minimizes the internal states of a processor, and provides for short instructions, it also suffers from at least the disadvantage of very high memory traffic, since the accumulator is the only temporary storage. The register based approach has the advantage of being the most general model for code generation, however, because of the access and related circuitry required to support a register, most prior art register based processors tend to provide only a limited number of registers, resulting in a relatively small working set. The disadvantage becomes especially limiting for heavily pipelined super-scalar processors.
Thus, a more efficient and effective approach to instruction execution without some of the disadvantages of the prior art approaches is desired.
SUMMARY OF THE INVENTION
One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.
In one embodiment, first one or more cache lines of cache locations are dynamically operated as registers of a first register set of a first virtual register file of a first architecture during a first time period, and as a second register of a second virtual register file of a second architecture set during a second time period. In another embodiment, second one or more cache lines of cache locations are dynamically operated as registers of the second register set of the second virtual register file of the second architecture during the second time period instead. In yet another embodiment, the first and second time periods, where the first and second one or more cache lines of cache locations are dynamically operated as registers of the first and second register sets of the first and second virtual register files of the first and second architectures, are the same time period. In each of these embodiments, the first and second virtual register files may be the same or different virtual register files, and if the first and second virtual register files are different virtual register files, the first and second architectures may be the same or different architectures.
REFERENCES:
patent: 4525780 (1985-06-01), Bratt et al.
patent: 4905141 (1990-02-01), Brenza
patent: 5287490 (1994-02-01), Sites
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430862 (1995-07-01), Smith et al.
patent: 5438668 (1995-08-01), Coon et al.
patent: 5568401 (1996-10-01), Narayanaswami
patent: 5574873 (1996-11-01), Davidian
patent: 5574927 (1996-11-01), Scantlin
patent: 5742802 (1998-04-01), Harter et al.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 3, entitled “Instruction Set Design: Alternatives and Principles”, pp. 89-137.
Computer Architecture and Quantitative Approach; Authors: John L. Hennessy, David A. Patterson; Morgan Kaufmann Publishers, Inc., 1990, Chapter 5, entitled “Basic Processor Implementation Techniques”, pp. 199-248.
Blakely , Sokoloff, Taylor & Zafman LLP
Brecis Communications
Cabeca John W.
Tran Denise
LandOfFree
Virtual register sets does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Virtual register sets, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual register sets will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2556278