Virtual output buffer architecture

Details Virtual output buffer architecture Virtual output buffer architecture

2006-06-14

2008-09-16

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S147000, C710S052000, C710S053000, C710S054000, C710S055000, C710S056000

Reexamination Certificate

active

07426604

ABSTRACT:
A buffer architecture enables linked lists to be used to administer virtual output queue buffering. The buffer has three random access memories (RAMs). A data RAM holds data. A free RAM holds a linked list of entries defining free space in the data RAM. Destination RAM holds a linked list of entries defining data in the data RAM to be forwarded to a destination.

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