Virtual multi-port RAM

Details Virtual multi-port RAM Virtual multi-port RAM

1992-04-23

1993-04-20

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Multiple port access

36518902, 36518903, 36523002, 36523003, 36518905, 36523008, 365233, 365203, 36518912, G11C 804

Patent

active

052048411

ABSTRACT:
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.

REFERENCES:
patent: 4937781 (1990-06-01), Lee et al.
patent: 4998223 (1991-03-01), Akaogi
patent: 5001671 (1991-03-01), Koo et al.
patent: 5003475 (1991-03-01), Kerber et al.
patent: 5007022 (1991-04-01), Leigh
"Special Application Memories"; 8172 IEEE International Solid-State Circuits Conference; 28 (1985) Feb.; 32nd Conf.; by Frank E. Barber, Daniel J. Eisenberg, Gloria A. Ingram, Mark S. Strauss and Thomas R. Wik; pp. 44-46.
"Pipelined Clocked Static Memory"; IBM Technical Disclosure Bulletin; vol. 32; No. 38, Aug. 1989, pp. 431-432.
"Pipelined, Time-Sharing Access Technique for a High Integrated Multi-Port Memory"; IEEE Symposium on VLSI Circuits; Jun. 1990; by Tsuneo Matsumura, Ken-ichi Endo and Junzo Yamada; pp. 107-108.
J. Rosenberg, "Dictionary of Computers, Information Processing, and Telecommunications", 2nd Edition, .COPYRGT.1987 John Wiley & Sons, Inc., QA 76,15,R67, pp. 467, 691-693.

Affiliated with

Also associated with

Rating

Virtual multi-port RAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Virtual multi-port RAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual multi-port RAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1530629