Virtual memory translator for real-time operating systems

Details Virtual memory translator for real-time operating systems Virtual memory translator for real-time operating systems

2007-04-03

2007-04-03

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S221000

Reexamination Certificate

active

10659922

ABSTRACT:
A multi-tiered lookup table is used to progressively map a virtual address to a specific control word that facilitates resolution of the virtual address for a translation lookaside buffer (TLB) miss. In one embodiment, the control word has a compressed and efficiently encoded image of the TLB hardware register data. The control word is accessed with or without a level of indirection in various embodiments. In some embodiments, the control word provides all information needed to decode the majority of memory blocks, or points to a third level for special blocks.

REFERENCES:
patent: 5586283 (1996-12-01), Lopez-Aguado et al.
patent: 5696925 (1997-12-01), Koh
patent: 6643759 (2003-11-01), Andersson et al.

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