Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1995-10-10
2000-08-08
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711202, 711205, 711206, G06F 1202
Patent
active
061015903
ABSTRACT:
A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Local-to-global virtual translation is performed by either mapping local virtual addresses to a single global virtual address space or to multiple global virtual address spaces. The local-to-global virtual translator includes a cell which corresponds to each local address space for performing the translations. In a memory system in which both data and instruction address accesses are performed, separate cache and tag structures are employed for handling each of the data and instruction memory accesses. In addition, the cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit, cache miss, or buffer access occurs during a given data or instruction access. In addition, the cache is configurable such that it can be configured into a buffer portion or a cache portion for faster cache accesses. Memory area privilege protection is also achieved by employing a gateway instruction which generate an address to access a gateway storage area. The gateway storage area holds pointers to both an instruction area and a data area. The gateway instruction branches to the instruction area and loads the pointer to the data area.
REFERENCES:
patent: 4442484 (1984-04-01), Childs, Jr. et al.
patent: 4539637 (1985-09-01), DeBruler
patent: 5226133 (1993-07-01), Taylor et al.
patent: 5247629 (1993-09-01), Casamatta et al.
patent: 5303378 (1994-04-01), Cohen
patent: 5319760 (1994-06-01), Mason et al.
patent: 5390310 (1995-02-01), Welland
patent: 5430850 (1995-07-01), Papadopoulus et al.
Micro Unity Systems Engineering, Inc.
Nguyen Than
Yoo Do Hyun
LandOfFree
Virtual memory system with local and global virtual address tran does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Virtual memory system with local and global virtual address tran, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Virtual memory system with local and global virtual address tran will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1160480