Virtual memory system for vector based computer systems

Electrical computers and digital processing systems: memory – Address formation – Address mapping

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711128, 711208, 39580002, 395563, G06F 1210, G06F 1576

Patent

active

058955011

ABSTRACT:
A virtual memory management system for a vector based processing system detects early page or segment faults allowing pipelined instructions to be halted and resumed once the pages or segments required for a job are available in main storage. A multiplier is used for stride accesses, and min and max registers are used for gather/scatter instructions to provide a range of addresses to be accessed during a job. These ranges are determined early enough in execution of instructions related to a job to allow saving the state of the processor and resuming execution of the instructions once the data is available in main storage.

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patent: 4768146 (1988-08-01), Nagashima et al.
patent: 4991083 (1991-02-01), Aoyama et al.
patent: 5063497 (1991-11-01), Cutler et al.
patent: 5430856 (1995-07-01), Kinoshita

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