Virtual-ground, split-gate flash memory cell arrangements...

Details Virtual-ground, split-gate flash memory cell arrangements... Virtual-ground, split-gate flash memory cell arrangements...

2000-12-19

2003-02-11

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000, C257S900000, C365S185010

Reexamination Certificate

active

06518619

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is in the field of flash memory cells provided with split-gates and having a virtual ground arrangement.
Several patents have proposed to use split-gate arrangements in flash memory cells, e.g., U.S. Pat. No. 5,268,585, U.S. Pat. No. 5,338,952, U.S. Pat. No. 5,414,286, U.S. Pat. No. 5,587,332, U.S. Pat. No. 5,614,747, WO/99/13513, and JP-A-07/130884. Of these prior art documents, U.S. Pat. No. 5,338,952 also discloses a virtual-ground arrangement of such split-gate memory cells. This known virtual ground arrangement will be summarized below.
FIG. 1
, which corresponds to
FIG. 7
of U.S. Pat. No. 5,338,952, shows two split-gate memory cells C
11
, C
12
in a virtual ground arrangement. Memory cells C
11
, C
12
are built on a p-type Si substrate
1
. Three n
+
diffusion layers
8
are shown. The left-hand n
+
layer
8
operates as a drain to memory cell C
11
. The middle diffusion layer
8
operates as a source to memory cell C
11
and as a drain to memory cell C
12
. The right-hand diffusion layer
8
operates as a source to memory cell C
12
(and may operate as a drain to a further memory cell, not shown, at the right-hand side of memory cell C
12
). Since adjacent memory cells share a source/drain diffusion layer, this arrangement is referred to as “virtual ground”.
A first SiO
2
gate oxide film
2
is present on the substrate
1
between a selection gate
4
and the substrate
1
. A rather thick second insulating layer
5
of SiO
2
is located on top of the selection gate
4
. A floating gate
11
is located adjacent to the selection gate
4
, and separated from the substrate
1
by a tunnel oxide film
9
made of SiO
2
. The floating gate
11
is surrounded by an insulating film to insulate the floating gate from any other conducting element.
On top of the entire structure, as shown in
FIG. 1
, a control gate
13
is formed.
FIG. 2
, which corresponds to
FIG. 6
of U.S. Pat. No. 5,338,952, shows an equivalent electric circuit of four memory cells C
11
, C
12
, C
21
, C
22
in a virtual ground connection scheme. In
FIG. 2
, the following reference signs are used. Reference sign CG
1
refers to a control gate line interconnecting control gates
13
of memory cells C
11
, C
12
as shown in FIG.
1
. Reference sign CG
2
refers to a control gate line interconnecting control gates of memory cells C
21
, C
22
. Reference signs SG
1
and SG
2
refer to selection gate lines interconnecting selection gates of memory cells C
11
, C
21
, and C
12
, C
22
, respectively. Reference sign BL
1
refers to a bit line interconnecting the drains of memory cells C
11
, C
21
. Reference sign BL
2
refers to a bit line interconnecting both the sources of memory cells C
11
, C
21
and the drains of memory cells C
12
, C
22
. Reference sign BL
3
refers to a bit line interconnecting the sources of memory cells C
12
, C
22
.
For programming, erasing, and reading e.g. memory cell C
21
, the following voltages on the control gate lines CG
1
, CG
2
, the selection gate lines SG
1
, SG
2
, and the bit lines BL
1
, BL
2
, BL
3
apply (Table 1).
TABLE 1
Write, erase, and read voltages for memory arrangement of
FIG. 2
BL1
BL2
BL3
CG1
CG2
SG1
SG2
writing
+5 V
 0 V
0 V
 0 V
+12 V
+2 V
0 V
erasing
+5 V
+5 V
0 V
−11 V
−11 V
 0 V
0 V
reading
+2 V
 0 V
0 V
 0 V
 +5 V
+5 V
0 V
Writing information into memory cells is carried out by means of the “Source Side Injection” (SSI) current mechanism. Erasing memory cells is done by “Folwer-Nordhein” (FN) tunneling.
As already referred to in U.S. Pat. No. 5,338,952, a problem during reading memory cell C
21
may arise due to over-erasure of memory cell C
11
. Over-erasure of memory cell C
11
may occur during erasing cell C
11
and refers to too large an amount of electrons being removed from the floating gate
11
such that, after the erasing procedure, floating gate
11
is effectively positively charged. Consequently, even though control gate line CG
1
is not charged during reading memory cell
21
, memory cell C
11
may still be slightly conducting since its selection gate
4
is also positively charged owing to selection line SG
1
being high. Thus, since bit line BL
1
is high and bit line BL
2
is low during reading memory cell C
21
, an undesired leakage current may flow through memory cell C
11
.
In order to solve this problem of over-erasure, U.S. Pat. No. 5,338,952 proposes to provide the individual memory cells with drain and source lines extending perpendicularly to one another, so that by generating suitable drain and source voltages only one desired memory cell will be selected.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a split-gate memory cell that solves the problem of over-erasure and that can be connected in a virtual ground arrangement in which source and drain lines are still parallel to one another.
This object is obtained by means of a memory cell according to the invention, comprising:
(a) a semiconductor substrate provided with a first diffusion layer and a second diffusion layer on a substrate surface;
(b) a floating gate insulating film on the substrate surface and a floating gate on the floating gate insulating film;
(c) a selection gate insulating film on the substrate surface and a selection gate on the selection gate insulating film;
(d) a control gate insulating film on the substrate surface and a control gate on the control gate insulating film;
the floating gate, selection gate and control gate being electrically insulated from one another, the first and second diffusion layers being arranged as a source and a drain of a field effect transistor structure, and the floating gate and selection gate being arranged as series field effect gates in the field effect transistor structure, and the control gate being arranged as a further field effect gate in the field effect transistor structure, in series with both the floating gate and the selection gate.
It is observed that, in this definition, “in series” refers to the different gates being arranged such that they are able to generate conducting channels in series with one another between the drain and the source of the memory cell transistor structure.
Such a memory cell may be termed a “three transistor flash memory cell” or a “double-split-gate flash memory cell”. The advantage of such a memory cell is that no conducting channel can be inadvertently generated between source and drain diffusion layers by an over-erased floating gate. It will always be necessary that the control gate voltage is also high enough to provide a conducting channel in the substrate below the control gate in series with the conducting channel in the substrate due to the selection gate voltage.
Advantageously, a plurality of such memory cells can be applied in a memory, wherein:
the memory cells are arranged in a plurality of rows and a plurality of columns, the rows extending in a row direction and the columns extending in a column direction;
the first diffusion layer extends in the column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in the column direction;
the second diffusion layer extends in the column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in the column direction;
selection gates of memory cells in a column of memory cells are interconnected by a selection gate line extending in the column direction;
control gates of memory cells in a row direction are interconnected by a control gate line extending in the row direction.
In such a memory, the sources of a column of memory cells are the drains of the memory cells of an adjacent column. Thus, the memory has a virtual ground structure. Moreover, the control gate line extends in a direction perpendicular to the source and drain lines, thus providing a unique selection of any memory cell during reading and avoiding that a conducting channel can be inadvertently

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