Virtual ground single transistor memory cell, memory array...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29300, C257S006000, C438S266000, C438S286000, C438S302000, C438S525000

Reexamination Certificate

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06873004

ABSTRACT:
An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

REFERENCES:
patent: 5060195 (1991-10-01), Gill et al.
patent: 5418741 (1995-05-01), Gill
patent: 5646886 (1997-07-01), Brahmbhatt
patent: 5959892 (1999-09-01), Lin et al.
patent: 6130134 (2000-10-01), Chen
patent: 6175519 (2001-01-01), Lu et al.

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