Virtual ground semiconductor memory device

Details Virtual ground semiconductor memory device Virtual ground semiconductor memory device

2003-03-19

2004-01-20

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185160, C365S185110, C365S230040, C365S063000

Reexamination Certificate

active

06680872

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a virtual ground type read only memory device.
2. Description of the Related Art
A virtual-grounded semiconductor memory device has been developed to reduce a chip area. Digit lines are commonly provided for plural memory cells. Sources and drains of adjacent memory cells are common to each other to reduce the number of drain contacts and source contacts, thereby reducing the chip area.
A bias voltage is applied across word and digit lines designated in accordance with an address signal, and a sense amplifier detects a current which flows through a designated memory cell for reading out an information stored in the designated memory cell. Further, a reference signal is supplied to a differential circuit for allowing the differential circuit to judge “0” or “1” for the information detected by the sense amplifier.
In case of a bank-selecting type virtual-grounded semiconductor memory device, configurations of signal lines, ground lines and pre-charge lines are changed upon changing the bank, whereby rising time of the digit lines is also changed. As a result, a time difference from the reference signal is caused.
If a designated bit is adjacent to two ON-bit lines, capacitances of diffusion layers of ON-bit cells are added to a current path, whereby the necessary sense amplifier current or reference current for charging-up the increased capacitance is temporary increased.
The technical term “ON-bit cell” means a cell transistor having a lower threshold voltage than a word line voltage. The technical term “OFF-bit cell” means a cell transistor having a higher threshold voltage than a word line voltage.
FIG. 1A
is a circuit diagram of a reference cell region of a conventional virtual-grounded semiconductor memory device. The reference cell region includes two bank selecting lines BS, and transistors Trb
0
, Trb
1
, Trb
2
, and Trb
3
. Gates of the transistors Trb
0
, Trb
1
, Trb
2
, and Trb
3
are connected to the bank selecting lines BS. Sources of the transistors Trb
0
, Trb
1
, Trb
2
, and Trb
3
are connected to digit lines. Drains of the transistors Trb
0
, Trb
1
, Trb
2
, and Trb
3
are commonly connected to reference digit lines RD
0
and RD
1
.
The reference cell region further includes word lines connected to an X-decoder which is not illustrated, and four ground selecting lines GS connected to gates of transistors Trg
0
, Trg
1
, Trg
2
, Trg
3
, and Trg
4
. Drains of the transistors Trg
0
, Trg
1
, Trg
2
, Trg
3
, and Trg
4
are connected to subordinate ground lines for the reference cells. Sources of the transistors Trg
0
, Trg
1
, Trg
2
and Trg
3
are commonly connected to a reference virtual ground line RVG
1
. A source of the transistor Trg
4
is connected to a reference virtual ground line RVG
2
.
The bank selecting lines BS and the ground selecting lines GS are independent from the X-decoder. In order to select a single bank BANK
3
, the bank selecting line and the ground selecting line are fixed at high level for placing the transistors Trb
1
and Trg
2
in ON-state.
The bank BANK
3
has the ON-bit cells and the remaining banks have the OFF-bit cells, for which reason the capacitances of the subordinate digit lines and the subordinate virtual ground lines of the remaining banks are not added.
FIG. 1B
is a diagram of time-dependent variations in voltage of selected digit lines and reference digit lines when a bank having OFF-bit cells is selected in the reference cell region of FIG.
1
A. The reference digit line is charged-up faster than the selected digit line. If the OFF-bit cell of the memory cell region is selected, the reading out operation from the OFF-bit cell is delayed. The delay in reading out operation may be caused depending on the bank. This delay may be so called to as bank dependency.
FIG. 2A
is a circuit diagram of another reference cell region of the conventional semiconductor memory device. The other reference cell region of
FIG. 2A
is structurally different from the above reference cell region of
FIG. 1A
in the following points. The bank selecting lines BS and the ground selecting lines GS are also connected to the X-decoder which is not illustrated. Further, all of the reference cells are ON-bit cells.
Changing the bank makes the bank-dependency of the flat cells to the memory cells. All of the cells on the same word line are thus ON-bit cells. The capacitances of the subordinate digit lines and the subordinate virtual ground lines are added through the adjacent ON-bit cells to the reference current path.
FIG. 2B
is a diagram of time-dependent variations of reference current IRA and sense amplifier current when a memory cell adjacent to OFF-bit cells is selected in the reference cell region of FIG.
2
A. If the sense amplifier current is transitionally insufficient, the reference current IRA is transitionally larger than the sense amplifier current ISA′. The judgement to the ON-bit cell by the differential circuit is delayed. The reading out speed or the ON-judgement speed by the sense amplifier is delayed depending on code patterns. This delay may be so called to as code pattern dependency.
In the above circumstances, the development of a novel semiconductor memory device free from the above problems is desirable.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel semiconductor memory device free of bank dependency.
It is a still further object of the present invention to provide a novel semiconductor memory device free of code pattern dependency.
It is yet a further object of the present invention to provide a novel semiconductor memory device exhibiting higher speed read-out operation.
The present invention provides a semiconductor memory device including: a memory cell region including main memory cells, main digit lines, and main virtual ground lines, and the memory cell region possessing a first current routine pattern through the main digit line to the main memory cell designated in accordance with a address signal; and a reference cell region including reference memory cells, reference digit lines, and reference virtual ground lines, and the reference cell region possessing a second current routine pattern through the reference digit line to the reference memory cell in accordance with the address signal, wherein the first current routine pattern is always identical with the second current routine pattern upon designating any memory cell addresses.


REFERENCES:
patent: 5875128 (1999-02-01), Ishizuka
patent: 5966327 (1999-10-01), Jo
patent: 6081474 (2000-06-01), Togami et al.
patent: 6310811 (2001-10-01), Kohno
patent: 6462986 (2002-10-01), Khan
patent: 6473327 (2002-10-01), Ishizuka

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