Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-06-14
2004-09-21
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S114000
Reexamination Certificate
active
06794902
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to logic circuits, and specifically relates to logic circuits having a virtual ground.
BACKGROUND OF THE INVENTION
A virtual ground circuit can be used to help the speed and power of a gate in dynamic circuits. In particular, replacing a clocked footer conventionally found at the bottom of an n-device stack in such circuits with a shared virtual ground saves power and increases performance.
SUMMARY OF THE INVENTION
Described herein is a system and method that utilizes three virtual ground pre-charge systems to improve the dynamic node charge time of a logical circuit. In particular, a logic circuit synchronized by a clock having an A (high) and a B (low) phase is described. The logic circuit includes a wired-OR device receiving a wired-OR voltage during the B phase of the clock, and a virtual ground connected to the wired-OR device via a digital network. The logic circuit also includes a voltage reducer for connecting a power-supply, supplying a power-supply voltage, to the virtual ground. The voltage reducer reduces the power-supply voltage supplied by the power-supply to the virtual ground during the B phase of the clock, and reduces the charge on the virtual ground, thereby increasing the speed and efficiency of the logic circuit.
Also described herein is a method for increasing the speed and efficiency of a logic circuit synchronized by a clock having an A and a B phase. The method includes providing a wired-OR device that, during the B phase of the clock, receives a wired-OR voltage. The method also includes connecting a virtual ground to the wired-OR device via a digital network, and, during the B phase of the clock, supplying a first power-supply voltage from a first power-supply to the virtual ground via a voltage reducer. The voltage reducer reduces the first power-supply voltage supplied by the first power-supply to the virtual ground, and reduces the charge on the virtual ground, thereby increasing the speed and efficiency of the logic circuit.
REFERENCES:
patent: 6366134 (2002-04-01), Deng
Becker Matthew E.
Fair, III Harry R.
Lamere Marc E.
White Jonathan A.
Canning Kevin J.
Chang Daniel D.
Lahive & Cockfield LLP
Sun Microsystems Inc.
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