Static information storage and retrieval – Read/write circuit
Patent
1995-03-14
1996-08-06
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
36518904, 36523003, 36523005, G11C 1300
Patent
active
055441041
ABSTRACT:
An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver devices, and interconnection means (17) for connecting the array of input buses to the array of output buses. The interconnection means include on the one hand, a third plurality of N3 switching memories (FIFO m) used as first-in, first-out FIFO devices provided with a write port (Din) and with a read port (Dout), and on the other hand, first control means (S[j,m],24a,24b) for connecting in a virtual manner the input port of at least one switching memory to a specified input bus, and second control means (S[k,m],24a',24b') for connecting in a virtual manner at least one output bus to the read port of the said switching memory, so that the said specified switching memory constitutes a temporary interconnection point, independent of the input buses and output buses to be interconnected. This interconnection-point memory enables Application to the asynchronous transfer of data between senders and receivers.
REFERENCES:
patent: 5109361 (1992-04-01), Yim et al.
Donaldson Richard L.
Fears Terrell W.
Hiller William E.
Texas Instruments Incorporated
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