Virtual computer system of multi-processor constitution

Details Virtual computer system of multi-processor constitution Virtual computer system of multi-processor constitution

1997-01-10

1999-04-20

Coleman, Eric

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711159, G06F 940

Patent

active

058965203

ABSTRACT:
A virtual computer system of a multi-processor arrangement reduces the overhead of XPTLB processing. The processing of a PTLB (translation look-aside buffer processing) is controlled using IP dispatch information about virtual computers that is stored a hardware share area (HSA). A control unit (CU) has a group of bit-map BIM (broadcast IP mask) latches which correspond to the configured IP's and in which the IP dispatch information is set upon purging of a translation look-aside buffer. Through AND gate logic provided in the CU, whether or not an IP is to receive a PTLB request is determined on the basis of the information set in the BIM masks. Specifically, the AND gates compute the logical AND of each of the BIM masks with the control line of a XPTLB REQ from an IP being dispatched by a particular virtual computer. The AND gates provide an XPTLB REQ output designating PTLB processing to the other IP's if the associated BIM mask is set in accordance with IP dispatch information indicating that an IP has been dispatched by that particular virtual computer in the past.

REFERENCES:
patent: 4849881 (1989-07-01), Eguchi
patent: 5317705 (1994-05-01), Gannon
patent: 5428757 (1995-06-01), Sutton
patent: 5574936 (1996-11-01), Ryba
"Instructions for the HITAC M Series Processors (M/ASA)," (8080-2-146, p. 253).

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