Virtual channel synchronous dynamic random access memory

Details Virtual channel synchronous dynamic random access memory Virtual channel synchronous dynamic random access memory

1999-07-02

2002-10-29

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S191000, C365S233100

Reexamination Certificate

active

06473828

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to “virtual” channel memories, and more particularly to the testing of such memories.
BACKGROUND OF THE INVENTION
Many computer systems can include a main storage. Typically, a main storage can include high capacity semiconductor devices that are relatively inexpensive. One such semiconductor device is a general purpose dynamic random access memories (DRAMs). A drawback to general purpose DRAMs is that such devices can have relatively slow operating speeds.
More recent computer systems can have increased operating speeds. In particular, computer system microprocessor unit (MPU) speeds have increased. While general purpose DRAM speeds have also increased, such increases in speed have generally not been sufficient to keep up with MPU speeds. Due to such operating speed differences, mainstream systems are usually equipped with a substorage device between a main storage and a MPU. Such substorage devices are typically referred to as “cache” memories. A cache memory can utilize a high-speed static RAM (SRAM), an emitter coupled logic bipolar RAM (ECLRAM), or other such storage devices.
A cache memory may be external to a MPU or may be built within a MPU. Recently however, some workstations or personal computers have included a semiconductor storage device having a main storage device formed from a DRAM and a cache memory formed from a high-speed SRAM. The DRAM and SRAM are formed on the same semiconductor substrate.
Prior art semiconductor devices have been disclosed in Japanese Patent Laid-Open Publication No. Sho 57-20983, Japanese Patent Laid-Open Publication No. Sho 60-7690, Japanese Patent Laid-Open Publication No. Sho 62-38590, Japanese Patent Laid-Open Publication No. Hei 1-146187. Since devices that include a DRAM and SRAM can use the SRAM as a cache, such devices are often referred to as cache DRAMs or CDRAMs.
CDRAMs can be arranged to transfer data between the DRAM and SRAM parts in a bi-directional fashion. When a memory is accessed, if the requested data location is in the SRAM portion, the access can be considered a cache “hit.” If a requested data location is not in the SRAM portion, the access can be considered a cache “miss.” A drawback to conventional CDRAMs is that a cache miss can result in a data transfer operation that can include some delay.
A number of prior art techniques have been proposed to address the above drawback to CDRAMs. A number of prior art semiconductor devices are set forth in Japanese Patent Laid-Open Publication Hei 4-252486, Japanese Patent Laid-Open Publication Hei 4-318389, and Japanese Patent Laid-Open Publication Hei 5-2872. These publications disclose CDRAMs having bi-directional transfer gate circuits between a DRAM portion and a SRAM portion. The bi-directional transfer gate circuits can have a latch or register function. With a latch or register function it can be possible to perform a data transfer from the SRAM portion to the DRAM portion and a data transfer from the DRAM portion to the SRAM portion at the same time.
Despite the advantages of the above references, such as Japanese Patent Laid-Open Publication Hei 4-318389 and the like, such approaches can have problems. One such problem is pin count. Because the DRAM portion and SRAM portion have their own respective address pins, the number of pins on a CDRAM can be much larger than those of a conventional DRAM. Therefore, a CDRAM device is not compatible with an ordinary DRAM or the like.
A second problem associated with conventional CDRAMs is the amount of area that may be needed to realize a data transfer circuit. Because the area available for such circuits can be limited, the number of transfer bit lines between a DRAM and SRAM portion can also be limited.
Due to the above constraints, the number of data bits that can be transferred at the same time between a DRAM portion and an SRAM portion on a CDRAM can be limited. As one example, the number of bits can be limited to 16 bits. Further, many CDRAMs avoid placing transfer lines in the same area as column select lines. As a result, the number of transfer lines can further be limited, as the available areas for such lines can have a limited width. As a general rule, the smaller the number of bits that can be transferred between DRAM and SRAM portions, the lower hit rate of the cache. One skilled in the art would recognize that lower cache hit rates lead to slower overall data access operations for a CDRAM.
One skilled in the art would recognize that a main storage can receive memory accesses from different controllers (masters). Such multiple masters can also adversely impact system speed. In order to increase the speed of a system without lowering the hit rate of a cache, even in the case of multiple masters, a novel virtual channel SDRAM. (VCSDRAM) has been developed by the present inventor. Such a VCSDRAM can include a main storage portion and a substorage portion. The substorage portion can be allocated into a plurality of access registers. Reference is made to Japanese Patent Laid-Open Publication Hei 11-86559 and Japanese Patent Laid-Open Publication Hei 11-86532.
Referring now to
FIG. 9
, a VCSDRAM according to the present inventor is set forth in a block schematic diagram. The VCSDRAM of
FIG. 9
is designated by the general reference character
900
, and is shown to include a command decoder circuit
902
, a main storage activating signal generating circuit
904
, a transfer operation start signal generating circuit
906
, a transfer operation control circuit
908
, an operation mode setting circuit
910
, a main storage control circuit
912
, a main storage portion
914
, a substorage portion
916
, and a data transfer portion
918
.
The command decoder circuit
902
can receive four command signals RASB, CASB, WEB and CSB as inputs, and generate a number of internal signals. Internal signals can include an active command signal
120
, a precharge command signal
122
, and a transfer command signal
124
.
The main storage activating signal generating circuit
904
can receive an active command signal
120
and a precharge command signal
122
and provide a main storage activating signal
128
.
The transfer operation start signal generating circuit
906
can receive a transfer command signal
124
and provide a transfer operation start signal
130
.
The transfer operation control circuit
908
can receive a transfer operation start signal
130
and provide a storage control signal
132
that can control a substorage portion
916
and a data transfer portion
918
. Once a data transfer operation has ended, the transfer operation control circuit
908
can activate a transfer reset signal
134
that is connected to the transfer operation start signal generating circuit
906
. An active transfer reset signal
134
can release the latched state of a transfer command within the transfer operation start signal generating circuit
906
.
The operation of the VCSDRAM will now be described in conjunction with FIG.
4
.
FIG. 4
is a timing diagram illustrating the operation of a VCSDRAM.
A command decoder circuit
902
can receive an active command, shown as “
401
,” and output an active command signal
120
. The main storage activating signal generating circuit
904
can receive the active command signal
120
and provide a main storage activating signal
128
on the basis of the active command signal
120
.
Next, a command decoder circuit
902
can receive a transfer command, shown as “
402
,” and output a transfer command signal
124
.
The transfer operation start signal generating circuit
906
can receive a transfer command signal
124
. The transfer command signal
124
can be latched and held, and a transfer operation start signal
130
can be activated (driven high).
Next, a transfer operation control circuit
908
can receive an active transfer operation start signal
130
and activate a storage control signal
132
(drive it high). The storage control signal
132
can control the substorage portion
916
and control the transfer of data by the data transfer porti

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