Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2000-12-12
2003-01-07
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S100000, C711S154000, C711S203000
Reexamination Certificate
active
06505287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a virtual channel memory access controlling circuit and in particular, to a virtual channel memory access controlling circuit for controlling a virtual channel memory (referred to as VCM) with a controlling method of the least recently used method (referred to as LRU).
2. Description of the Prior Art
Next, with reference to the accompanying drawings, a conventional VCM will be described.
FIG. 1
is a schematic diagram showing the concept of the VCM.
FIG. 2
is a block diagram showing the structure of a conventional memory system using the VCM. Referring to
FIG. 1
, VCM
60
has a plurality of channels
50
composed of registers, and a memory cell
51
is composed of a plurality of segments. Each of the channels
50
is connected to all the segments of the memory cell
51
. Each segment is a data access unit. In other words, any address of the memory cell
51
can be accessed through any channel. Each of the channels
50
is assigned a unique channel number.
Referring to
FIG. 2
, the memory system is composed of VCM
60
, virtual channel memory access controlling circuit
62
, and memory masters
67
,
70
, and
73
. The memory masters
67
,
70
, and
73
are processors that execute, for example, jobs.
The virtual channel memory access controlling circuit
62
performs reading/writing operations, i.e. foreground process, from/to the channels
50
. The virtual channel memory access controlling circuit
62
also performs internal operations such as a data transferring operation between the memory cell
51
and the channels
50
, a pre-charging operation, and a refreshing operation for the memory cell
51
, i.e. background process, independent from the foreground process. Since the virtual channel memory access controlling circuit
62
independently performs the foreground process and the background process, a high average data transfer rate for the VCM
60
can be accomplished.
The channels
50
of the VCM
60
and the virtual channel memory access controlling circuit
62
are connected by a dedicated memory bus
61
. The virtual channel memory access controlling circuit
62
comprises a memory interface controlling portion
63
, an arbiter portion
64
, channel information storing portions
65
,
68
, and
71
, and LRU controlling portions
66
,
69
, and
72
. The memory interface controlling portion
63
controls the memory bus
61
. The arbiter portion
64
arbitrates access requests issued from the memory masters
67
,
70
, and
73
. The channel information storing portions
65
,
68
, and
71
store information of the channels
50
of the VCM
60
. The LRU controlling portions
66
,
69
, and
72
control the channel information storing portions
65
,
68
, and
71
corresponding to the LRU controlling method.
The channel information storing portions
65
,
68
, and
71
and the LRU controlling portions
66
,
69
, and
72
are disposed corresponding to the memory masters
67
,
70
, and
73
, respectively, so as to fulfill the feature of the VCM
60
. To deal with multitask processes of the memory masters
67
,
70
, and
73
, proper numbers of channels
50
are assigned to the memory masters
67
,
70
, and
73
so as to shorten the access wait times of the memory masters
67
,
70
, and
73
. In that example, as shown in
FIG. 2
, it is assumed that three channels
50
are assigned to the memory master
67
; two channels
50
are assigned to the memory master
70
; and four channels
50
are assigned to the memory master
73
. In that case, the channels
50
are not redundantly assigned to a plurality of memory masters. Thus, the number of channels
50
is nine.
Next, the operation of the above-described virtual channel memory access controlling circuit
62
will be described. In the example, it is assumed that the memory master
67
reads data from the VCM
60
.
When the memory master
67
issues a read request to the arbiter portion
64
, the arbiter portion
64
arbitrates the read request issued from the memory master
67
with access requests issued from the memory masters
70
and
73
to the VCM
60
. The arbiter portion
64
permits the read request of the memory master
67
just after or in a predetermined time period after the memory master
67
has issued the read request. Thereafter, the memory master
67
designates a memory address that contains a bank address, a row address, a segment address, and a column address, and issues the read request with the designated address to the channel information storing portion
65
.
The channel information storing portion
65
determines whether the bank address, the row address, and the segment address in the memory address of the read request match those in any storage area of the channel information storing portion
65
. When the determined result is Yes, a channel hit takes place. When the determined result is No, a channel miss takes place. Each register of each channel
50
stores data of address groups designated by a bank address, a row address, and a segment address.
When a channel hit takes place, the memory address supplied from the memory master
67
to the channel information storing portion
65
is stored to a storage area corresponding to the hit channel. The LRU controlling portion
66
designates the hit channel as the lowest rank channel. In other words, the LRU controlling portion
66
designates the hit channel as the most recently used channel. In addition, the LRU controlling portion
66
upwardly shifts the ranks of the other channels by one.
On the other hand, when a channel miss takes place, the memory address supplied from the memory master
67
to the channel information storing portion
65
is stored to a storage area of the highest rank channel. In addition, the LRU controlling portion
66
shifts the channel that has stored the memory address from the highest rank channel to the lowest rank channel. In other words, the LRU controlling portion
66
designates a channel to which a memory address is newly stored as a channel that was most recently used. In addition, the LRU controlling portion
66
upwardly shifts the ranks of the other channels by one.
The channel information storing portion
65
outputs a memory address stored in the storage area to the memory interface controlling portion
63
along with channel information. As a result, the memory interface controlling portion
63
generates a read cycle on the memory bus
61
.
FIG. 3
is a time chart showing the cases that a channel hit and a channel miss take place in a read cycle.
Referring to
FIG. 3
, PRE represents a pre-charge command that sends a bank address; ACT represents an activate command that sends a bank address and a row address; PFC is a pre-fetch command that sends a segment address and a channel number; and READ represents a read command that sends a channel number and a column address. When a channel miss takes place, namely, valid data to be read is stored in none of channels
50
, a bank that has been activated in the memory cell
51
is deactivated by a pre-charge command. Then, a row address at which valid data is stored is activated by an activate command. Then, the data is copied from the memory cell
51
to the channel
50
by a pre-fetch command. Then, the data is read from the channel
50
by a read command. On the other hand, in the case of a hit cycle, namely, data to be read is stored in a channel
50
, the cycle is completed with only a read command. As is clear from
FIG. 3
, the cycle time in the case of a channel miss takes place is longer than that in the case of a channel hit.
A prior art reference of JPA 7-221797 discloses a FIFO memory controlling system. The FIFO memory controlling system can be used in common with an information processing system having one channel of an information generating source that generates information at a high data generation frequency and another information processing having a plurality of channels of information generating sources that generate information at a low data genera
Sughrue & Mion, PLLC
Thai Tuan V.
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