Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1999-01-04
2001-06-26
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S117000, C711S118000, C711S119000, C711S123000, C708S513000, C708S518000, C712S022000, C712S222000
Reexamination Certificate
active
06253299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to data registers in central processing units and more particularly to using a memory element to expand the available set of data registers.
2. Description of the Related Art
Conventionally, a processor architecture defines the group of operations available to the user (e.g., the instruction set) and the method to access data for these operations (e.g., the register set). The architecture limits data accuracy and range because architected registers store operands and results in a specified number of bits.
An example of limited accuracy is that floating point units implement truncation or rounding to limit the mantissa to the number of bits specified by the architecture. Data range is limited by the architecture because the number of register bits is directly proportional (by a power of 2) to the number of unique values that it can represent.
Therefore, there is a conventional need for a method for the central processing unit (CPU) to operate on registers which are wider than the architected set but which maintain compatibility with the architecture to allow greater data precision and range. Furthermore, there is a conventional need for such a system to be scalable to cover emerging architectures such as Single Instruction Multiple-Data (SIMD).
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for processing data, the structure comprising a processing unit having a base cache, base general registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base general registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base general registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.
The base general registers have a first architecture and the virtual cache registers have a format associated with a second architecture. For example, the base general registers could have an X86 architecture and the virtual cache registers could have a data format associated with an SIMD architecture.
The base processing precision could comprise a first floating point accuracy and the selectable enhanced processing precision would comprise a second floating point accuracy greater than the first floating point accuracy.
The virtual cache registers include data from at least two complete sets of the base general registers. The base general registers comprise floating point data registers and the virtual cache registers include data from at least two of the floating point data registers.
The method of processing data comprises supplying instructions for processing data to a processing unit, processing the data in base general registers according to a base processing precision, and processing the data in virtual registers according to a selectable enhanced processing precision, wherein the base processing precision is determined by a base width of the base general registers and the selectable enhanced processing precision is determined by a virtual width of the virtual registers. The data is transferred to the expanded registers only through the base general registers
The processing of the data in virtual registers comprises supplying first data to the base general registers, moving the first data from the base general registers to a first half of a virtual register of the virtual registers, supplying second data to the base general registers, and moving the second data from the base general registers to a second half of the virtual register.
The base general registers comprise floating point registers, the processing the data in virtual registers comprising supplying data to the floating point registers, and moving the data from the floating point registers to a virtual register of the virtual registers.
An alternative method to move floating point data into virtual registers comprises supplying first floating point data to memory, moving the first floating point data to the base general registers, moving the first floating point data from the base general registers to a first half of a virtual register of the virtual registers, supplying second floating point data to memory, supplying the second floating point data to the base general registers, and moving the second floating point data from the base general registers to a second half of the virtual register.
The invention has the ability to process a wider range of integer numbers, floating point numbers and logical data patterns, provides greater accuracy on floating point arithmetic and allows greater parallelism that has potential for higher performance. Furthermore, the invention makes processors compatible with applications software written for base architecture and also software which utilizes data formats in other architectures. The present invention uses examples with SIMD architectures but it is scalable to cover emerging architectures.
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Smith Jack R.
Ventrone Sebastian T.
Williams Keith R.
An Meng-Al T.
International Business Machines - Corporation
Lin Wen-Tai
McGinn & Gibb PLLC
Shkurko, Esq. Eugene I.
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