Video signal receiver including display synchronizing signal...

Television – Synchronization – Automatic phase or frequency control

Reexamination Certificate

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Details

C348S547000, C348S512000, C348S458000

Reexamination Certificate

active

07969507

ABSTRACT:
A video signal receiver including a display synchronizing signal generation device and control method are disclosed. The video signal receiver includes: a video processor converting an input analog video signal into a digital signal; a display processor scaling the video signal converted at the video processor with an output resolution; a displaying unit displaying the video signal scaled by the display processor; a detecting unit detecting whether an input vertical synchronization signal (In V-sync) and an output vertical synchronization signal of the analog video signal match; a PLL (Phase Locked Loop) adjusting a pixel clock according to a detection result of the detecting unit; and a timing generating unit generating an output horizontal synchronization signal and the output vertical synchronization signal by use of the pixel clock adjusted by the PLL, and providing the generated output horizontal and output vertical synchronization signals to the display processor and the detecting unit. Accordingly, it is possible to prevent twitching and freezing of a screen, even though input and output frame rates do not correspond.

REFERENCES:
patent: 6316974 (2001-11-01), Taraci et al.
patent: 6674482 (2004-01-01), Park
patent: 2001-69082 (2001-07-01), None
patent: 2003-33828 (2003-05-01), None
patent: 2004-64943 (2004-07-01), None
patent: WO 2005/027515 (2005-03-01), None
patent: WO 2005/029845 (2005-03-01), None

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