Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1997-07-07
2001-04-17
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S182000, C345S182000
Reexamination Certificate
active
06219023
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for converting a low-resolution video signal supplied from a host into a video signal having a different-resolution, and a display device having such an apparatus.
2. Description of the Related Art
Each display device, such as an LCD (liquid crystal display) device, and a plasma display device has a plurality of pixels for displaying an image, whose brightness is controlled in accordance with video information provided from a host.
A typical active matrix LCD device, which is provided with an LCD control unit and an LCD panel, displays an image on the screen of the LCD panel in a such manner that pixels are turned on/off by means of switching elements corresponding respectively to the pixels. The LCD control unit converts analog color signals from a host (e.g., a personal computer) into digital color signals and generates a horizontal output signal Vout and a dot (i.e., pixel) clock signal Dclk by using horizontal and vertical synchronization signals from the host. The LCD panel has an LCD driving unit therein. The digital color signals, dot clock signals and horizontal output signals, which are provided from the LCD control unit, are supplied to the LCD driving circuit incorporated in the LCD panel.
An earlier LCD control unit, which is provided to control the LCD panel, has a PLL (phase lock loop) circuit and an ADC (analog-to-digital converter). When the PLL circuit receives a horizontal synchronization signal Hsync, it generates a horizontal output signal Hout and a dot clock signal Dclk. Also the ADC circuit converts analog color signals of R (red), G (green) and B (blue) from the host into digital color signals of R, G and B respectively, which are supplied to the LCD driving circuit. The horizontal output signal Hout is produced from the horizontal synchronization signal Hsync, and the frequency of the horizontal output signal Hout is equal to that of the horizontal synchronization signal Hsync being fed to the PLL circuit and may be changed in accordance with the kinds of host, and the PLL circuit outputs a horizontal output signal Hout having the predetermined polarity. For example, in the earlier LCD device having the driving circuit which is operated in synchronism with a horizontal output signal Hout having a negative polarity, even though the horizontal synchronization signal Hsync of a positive polarity from the host is supplied to the PLL circuit in the LCD device, the PLL circuit supplies the horizontal output signal Hout of a negative polarity for the LCD driving circuit. The PLL circuit, as is well known in the art, has a phase sensor, a voltage controlled oscillator (VCO), a divider, and an output generator.
In general, the earlier LCD device embodies a single display mode, for example, a Video Graphics Array (VGA) mode, a Super VGA (SVGA) mode or an extended Graphics Array (XGA) mode. Accordingly, if the VGA mode video signals of 640×480 active resolution are provided to the XGA mode supporting LCD device having an active resolution of 1024×768, an image is displayed on only a partial area “A” of the LCD screen, and is not displayed on the remaining area “B”. If SVGA mode signals having an active resolution of 800×600 are also provided to the XGA LCD device, the results are similar to the above case. Thus, one of several problems in the earlier LCD device is that, if low-resolution display mode signals from the host are fed to an LCD device capable of supporting a high-resolution display mode, an image is displayed on only a portion of only the LCD screen.
The following patents each disclose features in common with the present invention but do not teach or suggest the specifically recited features of the present invention: U.S. Pat. No. 5,528,740 to Hill et al., entitled Conversion Of Higher Resolution Images For Display On A Lower-Resolution Display Device, U.S. Pat. No. 5,535,018 to Yamano et al., entitled Information Processing Apparatus, U.S. Pat. No. 5,557,691 to Izuta, entitled Image Processing System, U.S. Pat. No. 5,568,597 to Nakayama et al, entitled Adapting Image Data Resolution To Match Resolution Of An Output Device, U.S. Pat. No. 5,612,715 to Karaki et al., entitled System And Method For Dynamically Adjusting Display Resolution Of Computer Generated Displays, U.S. Pat. No. 5,301,265 to Itoh, entitled Apparatus For Converting N Picture Elements To M Picture Elements, and U.S. Pat. No. 5,471,563 to Dennis et al., entitled System And Method For Automatic Resolution Reduction.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a video signal converting apparatus which may convert a low-resolution video signal from a host into a different-resolution video signal capable of being displayed on the entire screen of a high-resolution supporting display device.
It is another object of the present invention to provide a display device in which, even though low-resolution display mode signals from a host are provided to the display device, the low-resolution display mode signals may be displayed on the entire screen thereof.
According to an aspect of the present invention, a liquid crystal display (LCD) device is provided to receive horizontal and vertical synchronization signals and at least one analog video signal synchronized with said horizontal video signal from a host and to display an image on a screen thereof. The LCD device comprises: a display mode discriminating means for discriminating a display mode supported by said host in response to said horizontal and vertical synchronization signals to generate first and second mode signals and first, second, third, fourth and fifth data signals related to said discriminated display mode; a clock generator for generating first and second pixel clock signals in synchronism with said horizontal synchronization signal, said first and second pixel clock signals having frequencies corresponding to said first and second data signals, respectively, a pulse number of said first pixel clock signal corresponding to one horizontal line being equal to a value of said first data signal, and a pulse number of said second pixel clock signal corresponding to one horizontal line being equal to a value of said second data signal; an analog-to-digital converter (ADC) for converting said at least one analog video signal into a digital video signal in synchronism with said first pixel clock signal; a memory for storing said digital video signal; a horizontal output generator for receiving said third and fourth data signals in response to said vertical synchronization signal and for generating a horizontal output signal, said digital video signal being read from said memory in synchronism with said horizontal output signal, a pixel number per one cycle of said horizontal output signal being equal to a value of said third data signal, and a pixel number per one cycle of said horizontal output signal being equal to value of said third data signal, and a pixel number per a pulse width of said horizontal output signal being equal to a value of said fourth data signal; and a memory controller for controlling reading and storing operations of said memory in accordance with said horizontal synchronization signal, said horizontal output signal, said third and fifth data signals, and said first and second pixel clock signals, said reading operation being delayed from a rising edge of said horizontal synchronization signal to a period corresponding to a value of said fifth data signal and then activated, whereby said reading and storing operations are not simultaneously activated.
According to the other aspect of the present invention, an apparatus for converting analog video signals of a first display into digital video signals of a second display, comprises: a memory for storing said digital video signals; a horizontal output generator for receiving first and second data signals and a horizontal synchronization signal and for generating a horizontal output signal for enabling said
Blackman Anthony J.
Bushnell , Esq. Robert E.
Hjerpe Richard A.
Samsung Electronics Co,. Ltd.
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