Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reissue Patent
2002-03-14
2004-08-24
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S213000, C345S531000
Reissue Patent
active
RE038568
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from two applications entitled A Video Signal Converting Apparatus and a Display Device Having the Same earlier filed in the Korean Industrial Property Office on Apr. 17, 1996 and Dec. 10, 1996, and there duly assigned Ser. No. 96-11554 and 96-64026, respectively, by that Office.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for converting a low-resolution signal applied from a host into a video signal having different-resolution, and a display device having the same.
2. Background Art
Display devices, such as a liquid crystal display (LCD) device and plasma display device, have a plurality of pixels for displaying an image, wherein the pixel brightness is controlled in accordance with video information provided from a host.
An exemplary active matrix LCD device, which is provided with an LCD control unit and an LCD panel, displays an image on the screen of the LCD panel in a such manner that pixels are turned on/off by means of switching elements corresponding respectively to the pixels. The LCD control unit converts analog color signals from a host (e.g., a personal computer) into digital RGB color signals and generates a horizontal output signal, a vertical output signal and a dot (i.e., pixel) clock signal in response to horizontal synchronization signals and vertical synchronization signals from the host. The LCD panel has an LCD driving unit therein. The digital RGB color signals, dot clock signal, horizontal output signals and vertical output signals, which are provided from the LCD control unit, are supplied to the LCD driving circuit incorporated in the LCD panel.
An exemplary LCD control unit, which is provided to control the LCD panel, has a phase locked loop (PLL) circuit and an analog-to-digital converter (ADC). When the PLL circuit receives a horizontal synchronization signal, it generates a horizontal output signal and a dot clock signal. Also the ADC circuit converts analog color signals of R (red), G (green) and B (blue) from the host into digital color signals of R, G and B, respectively, which are supplied to the LCD driving circuit. The horizontal output signal Hout is produced from the horizontal synchronization signal, and the frequency of the horizontal output signal is equal to that of the horizontal synchronization signal. Meanwhile, the polarity of the horizontal synchronization signal being fed to the PLL circuit may be changed in accordance with the kinds of the host, and the PLL circuit outputs the horizontal output signal having a predetermined polarity. For example, in the LCD device having the driving circuit which is operated in synchronization with the horizontal output signal having negative polarity, even though the horizontal synchronization signal of positive polarity from the host is supplied to the PLL circuit in the LCD device, the PLL circuit supplies the horizontal output signal of negative polarity for the LCD driving circuit. The PLL circuit, as well known in the art, has a phase detector, a voltage controlled oscillator (VCO), a divider, and an output generator.
In general, the exemplary LCD device embodies a single display mode, for example, Video Graphics Array (VGA) mode, Super VGA (SVGA) mode or extended Graphics Array (XGA) mode. Accordingly, if the VGA mode video signals of 640×480 active resolution are provided to the XGA mode supporting LCD device having the active resolution of 1024×768, an image is displayed on only a partial area of the LCD screen, and is not displayed on the screen's remaining area. If the SVGA mode signals having the active resolution of 800×600 are also provided to the XGA LCD device, the results are similar to the above case. Thus, one of several problems in the exemplary LCD device, if low-resolution display mode signals from the host are fed to an LCD device capable of supporting high-resolution display mode signals, is that an image is partially displayed on the LCD screen.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a video signal converting apparatus which may convert a low-resolution video signal from a host into a different-resolution video signal capable of being displayed on the entire screen of a high-resolution supporting display device.
It is another object to provide a display device in which, even though low-resolution display mode signals from a host are provided to the display device, the low-resolution display mode signals may be displayed on the entire screen thereof.
According to an aspect of the present invention, a liquid crystal display (LCD) device receives horizontal, and vertical synchronization signals and at least one analog video signal synchronized with said horizontal video signal from a host and displays an image on a screen thereof. The LCD device comprises a display mode discriminating means for discriminating a display mode supported by the host in response to horizontal and vertical synchronization signals to generate first and second mode signals and first, second, third and fourth data signals related to a discriminated display mode. A clock generator generates first and second pixel clock signals in synchronization with the horizontal synchronization signal, and the first and second pixel clock signals have frequencies corresponding to first and second data signals, respectively. The pulse number of the first pixel clock signal corresponding to one horizontal line is equal to a value of the first data signal and the pulse number of the second pixel clock signal corresponding to one horizontal line is equal to a value of the second data signal. An analog-to-digital converter (ADC) converts at least one analog video signal into a digital video signal in synchronization with the first pixel clock signal. A memory for storing the digital video signal. A horizontal output generator for receiving third and fourth data signals in response to the vertical synchronization signal and generating a horizontal output signal, the digital video signal from the memory being in synchronization with the horizontal output signal, the pixel number per one cycle of the horizontal output signal being equal to a value of the third data signal, and the pixel number per a pulse width of the horizontal output signal being equal to a value of the fourth data signal. And, a memory controller is provided to enable the digital video signals to be stored in the memory in accordance with the mode signals, the horizonal synchronization signal and the first pixel clock signal, and enable the digital video signals stored in the memory to be read from the memory in accordance with the mode signals, the horizontal output signal and the second pixel clock signal.
In the embodiment, the memory comprises first, second and third memory blocks corresponding to R (red), G (green) and B (blue) data of the digital video signal each of the memory blocks having at least three line memories, each of which stores the corresponding digital R, G, B video signal from a corresponding ADC and corresponding to one horizontal line, and first, second and third multiplexers for selectively outputting data of the line memories of the corresponding memory block in response to a data selection signal from the memory controller. The memory controller comprises a flag generator for generating a plurality of flag signals indicative of the line memories into or from, which the digital video signal is stored or read, a memory selector for generating the first and second memory selection signals selecting the line memories in response to the flag signals to block simultaneous read and write operations of each memory line, and a memory operation control circuit for receiving the horizontal, and vertical synchronization signals and the first and second pixel clock signals, and controlling an access operation to the memory by means of the memory selector. The memory, the horiz
Bella Matthew C.
Blackman Anthony J
Bushnell , Esq. Robert E.
Samsung Electronics Co,. Ltd.
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