Computer graphics processing and selective visual display system – Computer graphics display memory system – For storing compressed data
Reexamination Certificate
1998-08-06
2002-03-19
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Computer graphics display memory system
For storing compressed data
Reexamination Certificate
active
06359625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to systems and methods of video display, and more particularly to systems and methods of pixel data compression in a computer system.
2. Description of Related Art
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application.
Over the last decade, the quality of computer graphic displays has steadily increased with improvements in pixel resolution, color depth, and screen refresh rate of the display device—typically a cathode ray tube (CRT) or a liquid crystal display (LCD). It is commonplace for graphics in computers to have a frame resolution of up to 1280×1024 pixels and up to 16.7 million simultaneous colors. Display of such high resolution and high color content images, particularly at high refresh rates, places great demands on the memory subsystem which stores the frame buffer. Typically, tradeoffs are made to obtain suitable display rates and resolutions which the memory subsystem can supply while still having enough bandwidth to perform memory accesses required by the graphics engine or host central processing unit (CPU). If the display data rate is too high, the system is paralyzed by constant pixel data reads from memory—leaving no time for other tasks to access the memory.
To illustrate this point, a computer system employing an inexpensive graphics subsystem, for example a memory array with 32-bit wide DRAMs having a “fast-page” access of 45 nanoseconds, would have a theoretical peak available bandwidth of 89 megabytes/second. Realistically however, this value must be de-rated to account for, inter alia, page misses—imposing an available bandwidth of about 77 megabytes/second. With a frame resolution of 1024×768 pixels, eight color intensity bits per pixel, and a seventy-five Hz refresh rate, the required display bandwidth is 59 megabytes/second (1024×768×1 Byte×75)−seventy-seven percent of the total available memory bandwidth. If the color intensity resolution were increased to sixteen bits per pixel, the display bandwidth requirement would double to 118 megabytes/second−29 megabytes/second more than the peak available bandwidth.
One approach in confronting these limitations is to simply increase the bandwidth of the memory subsystem by using special purpose dual-ported memories or by increasing the width of the DRAM interface. Accordingly, several types of specialty graphics memory integrated circuits have spawned such as dual-ported VRAM or Windows™ RAM. These types of memories however, are not produced in as large of volumes as the ubiquitous DRAM used for main memory, thus command a price premium.
By way of further background, power consumption is yet another major concern in the design of graphic display subsystems, especially in portable computers due to their limited battery life. It is known that power consumption increases in proportion with consumed memory bandwidth and thus high resolution and high color content display modes traditionally have not been well suited for portable computer applications.
From the foregoing, it can be seen that there is a need for a system and method for high performance graphics display without increased power consumption.
SUMMARY OF THE INVENTION
To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, a low power, reduced bandwidth, graphics display system and method is disclosed for generating pixel data utilizing full and compressed frame buffers. As pixel data is sent from the full frame buffer to a display device, it is concurrently compressed and captured in the compressed frame buffer so that subsequent unchanged frames are regenerated directly from the compressed frame buffer. Coherency is maintained between the full and compressed frame buffers with a dirty/valid tag RAM so that as the pixel data stream is transferred out and compressed, the compressed data is validated for subsequent frame updates from the compressed frame buffer.
Once the pixel data stream has been compressed, stored in the compressed frame buffer, and validated, on subsequent frames, the pixel data is retrieved directly from the compressed frame buffer and decompressed as it is sent to the display device. The pixel data is continuously retrieved as required to refresh the display from the compressed frame buffer until the compressed data elements are invalidated by future frame buffer writes. As new pixel data is rendered to the full frame buffer by a graphics engine or host CPU, the dirty tags for the corresponding compressed data elements are set so that during the next qualified frame scan, the pixel data is retrieved from the full frame buffer rather than the compressed frame buffer.
A feature of the present invention is separate dirty and valid bits to validate each compressed data element (preferably although not exclusively a raster line) in a frame and a programmable frame rate control mechanism to quality the dirty bits. The dirty bits are set in response to pixel data being rendered to the full frame buffer. The valid bits are set in response to the data compressor updating a compressed data element in the compressed frame buffer. The programmable frame rate control mechanism provides a programmable sample rate to qualify the dirty bits so that updates to the full frame buffer are ignored for a predetermined period of time and more frame displays occur from the compressed frame buffer, thus lowering memory bandwidth and power consumption.
Another feature of the present invention is the ability to employ unified memory in a practical graphics system—providing easy upgradeability for either graphics or main memory with the addition of continuous DRAM.
These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described specific examples of systems and methods practiced in accordance with the present invention.
REFERENCES:
patent: 5450130 (1995-09-01), Foley
patent: 5512921 (1996-04-01), Mital et al.
patent: 5586285 (1996-12-01), Hasbun et al.
patent: 5936616 (1999-08-01), Torborg, Jr. et al.
patent: 5987214 (1999-11-01), Iwamura
National Semiconductor Corporation
Shankar Vijay
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