Video frame storage system

Static information storage and retrieval – Addressing – Combined random and sequential addressing

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Details

36523008, 365236, G11C 800

Patent

active

050938070

ABSTRACT:
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

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