Video FIFO overflow control method that blocks video encoder dat

Details Video FIFO overflow control method that blocks video encoder dat Video FIFO overflow control method that blocks video encoder dat

1997-08-01

2000-02-01

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

348419, 370517, G06F 1314

Patent

active

06021449&

ABSTRACT:
A multimedia terminal having a host processor, an audio and video encoder and a system time clock. The encoders are input as digital video elementary frames into a multiplexer. The multiplexer includes a mux processor, a video FIFO and a video mux logic circuit coupled to both the mux processor and the video FIFO. Mux logic is operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in the FIFO to form the payload of a transport packet.

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