Boots – shoes – and leggings
Patent
1985-05-17
1986-12-09
Perkey, William B.
Boots, shoes, and leggings
364900, 340703, 340799, G06F 1562, G09G 102, G09G 128
Patent
active
046284672
ABSTRACT:
A video display control system comprises a video display processor (VDP) which is capable of accessing to a video RAM (VRAM) at an extremely high-speed. The VRAM used in this system comprises first and second dynamic RAMs each having an address input terminal to which row address data and column address data are supplied, a row address strobe input terminal, a column address strobe input terminal, and a data input/output terminal. The row address data is latched at the leading edge of a row address strobe signal applied to the row address strobe input terminal, while the column address data is latched at the leading edge of a column address strobe signal applied to the column address strobe input terminal. An access to an address of each dynamic RAM is established when both of the row and column address data are latched. The VDP comprises a VRAM interface for controlling an access to the first and second dynamic RAMs which is connected to the RAMs through a common address bus. The VRAM interface first outputs row address data together with a row address strobe signal RAS and then outputs column address data together with two column address strobe signals CAS0 and CAS1 which are rendered active in sequence and supplied to the first and second dynamic RAMs, respectively.
REFERENCES:
patent: 4149152 (1979-04-01), Russo
patent: 4511965 (1985-04-01), Rajaram
patent: 4574277 (1986-03-01), Krause et al.
Boisvert, Conrad J., "Doubling the Character Rate Handled by CRT Controllers", Electronics, vol. 52, No. 21, Oct. 11, 1979, pp. 155-157.
Myers, Ware, "Computer Graphics: Reaching the User", Computer, vol. 19, No. 3, Mar. 1981, pp. 7-17.
Ishii Takatoshi
Morimoto Minoru
Nishi Kazuhiko
Okumura Takatoshi
Yamaoka Shigemitsu
Ascii Corporation
Nippon Gakki Seizo Kabushiki Kaisha
Perkey William B.
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