Television – Two-way video and voice communication – Transmission control
Reexamination Certificate
1998-06-16
2002-08-27
Nguyen, Duc (Department: 2643)
Television
Two-way video and voice communication
Transmission control
C348S014010
Reexamination Certificate
active
06441842
ABSTRACT:
RELATED APPLICATIONS
This application is also related to, and fully incorporates by reference, U.S. patent application Ser. No. 08/708,184, entitled “Video Compression and Decompression Arrangement Having Reconfigurable Camera and Low-Bandwidth Transmission Capability”, filed Sep. 6, 1996, which is a continuation-in-part of U.S. patent application Ser. No. 08/457,516, entitled “Integrated Multimedia Communications Processor and Codec”, filed May 31, 1995 (now abandoned).
FIELD OF THE INVENTION
The present invention relates to video communication systems, and more particularly, to a programmable videocommunication device.
BACKGROUND OF THE INVENTION
Applications such as video telephone, digital television, and interactive multimedia using such digital storage technology as CD-ROM, digital audio tape, and magnetic disk require digital video coding, or video compression, to achieve the necessary high data transfer rates over relatively low bandwidth channels. Various standards have been proposed for video coding. A standard for the storage and transmission of still images has been adopted by the International Standards Organization (“ISO”), Joint Photographic Expert Group (“JPEC); see “JPEC Technical Specification, Revision 5,” JPEG-8-R5, January 1980. A standard for digital television broadcast coding at 30/45 Mb/s is under consideration; see CCIR-CMTT/2, “Digital Transmission of Component-Coded Television Signals at 30-34 Mb/s and 45 Mb/s Using the Discrete Cosine Transform,” Document CMTT/255. A standard for video telephony and video conferencing at 64 to 1920 kb/s has been adopted by the International Consulative Committee for Telephone and Telegraph (“CCITT”); see “Draft Revision of Recommendation H.261,” Document 572, CCITT SG XV, Working Party XV/1, Spec. Grp. on Coding for Visual Telephony. A standard for storage applications below 1.5 Mb/s, which are similar to the applications targeted by the CCITT standard, is under consideration by the Moving Picture Expets Group (“MPEG”) of the ISO. Video coding algorithms have been proposed as contributions to the standardization activity of ISO/MPEG; see Wong et al., “MCPIC: A Video Coding Algorithm for Transmission and Storage Applications,” IEEE Communications Magazine, November 1990, pp. 24-32.
While building block implementations of video arrangements have met with some success, a need has arisen for a programmable, high performance, and low cost digital signal processing arrangement suitable for stand alone use in image and video discrete cosine transform (“DCT”)-based compression and/or decompression systems. Programmability is desirable because of the wish to accommodate a variety of different existing algorithms, custom versions of existing algorithms, and future algorithms. High performance and low cost are desirable because of the price-performance demands of the highly competitive marketplace in which digital signal processing devices are sold.
SUMMARY OF THE INVENTION
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to one embodiment, a videocommunication apparatus for communicating video data over a telephone line, comprises: a video source configured and arranged to capture images and to generate video data representing the images; a telephone line interface circuit, including a signal transmission circuit and a signal receiver circuit, configured and arranged to transmit and receive video data over the telephone line; a memory circuit configured and arranged for storing executable code for controlling operation of the videocommunication apparatus, for storing executable code for compressing and decompressing video data consistent with at least one video-coding recommendation, and for storing executable code for processing pixels for a certain display type; a programmable processor circuit configured and arranged for executing the code for processing pixels for a certain display type and, in response, causing image data to be output for display, the programmable processor circuit having a first section, including a DSP-type processor, configured and arranged for executing the code for compressing and decompressing video, and further having a controller section, including a RISC-type processor, communicatively coupled to the first section and configured and arranged to execute the code for controlling operation of the videocommunication apparatus; and a display driver circuit responsive to the programmable processor circuit and configured and arranged to generate video data for a display.
In another embodiment of the present invention, the above videocommunication apparatus has the first section of the programmable processor circuit configured to include a data-flow path having an integrated arrangement of discrete circuits including multiplexers, multiplier-accumulators and an arithmetic logic unit, and wherein the multiplexers, multiplier-accumulators and the arithmetic logic unit are configured and arranged for both determining a motion vector displacement and a prediction error and for executing discrete-cosine transformation and quantization operations.
In yet other embodiments of the present invention: the first section of the programmable processor circuit includes a data-flow path having an integrated arrangement of discrete circuits including multiplexers, multiplier-accumulators and an arithmetic logic unit; the memory circuit is further configured and arranged to include multiple memory sections, the multiple memory sections arranged to be accessed in a memory hierarchy to permit the integrated arrangement of discrete circuits to execute discrete-cosine transformation operations on a first set of data while a second set of data is input to the integrated arrangement of discrete circuits; and the first section of the programmable processor circuit includes a data-flow path having an arithmetic logic unit that is programmable reconfigurable for either a pixel mode or a word mode.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
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Fandrianto Jan
Martin Bryan R.
Rainnie Hedley K. J.
Sutardja Sehat
Wang Chi Shin
8×8, Inc.
Eng George
Nguyen Duc
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