Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1998-12-11
2004-04-13
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S543000, C345S538000, C710S056000, C711S158000
Reexamination Certificate
active
06720968
ABSTRACT:
DESCRIPTION OF THE RELATED ART
The problem of acquiring video data into computer system memory (i.e. the main memory of a computer system) is increasingly the subject of attention in the field of image/video processing. As the performance of software image processing increases in response to improvements in CPU capacity, it is increasingly necessary to provide for fast and efficient acquisition of video frames from video source devices. Typical video sources include industrial cameras, camcorders, video cameras, VCRs, TV tuners, and laserdisk players.
Typically, a host computer system employs a video acquisition board to perform video frame acquisition. A video acquisition board is generally equipped with (a) an analog video port for coupling to an analog video source, (b) an A/D converter, (c) a frame acquisition buffer [RAM], (d) a bus connection to the host system, and (e) a DMA controller. In addition, a video board is often equipped with a digital video port for coupling to a digital video source.
An analog video source provides an analog video signal to the video board via the analog video port. The analog video signal is organized as a stream of video frames with a typical rate of 30 frames per second. The video board employs the A/D converter to digitize the analog video signal in response to synchronization information embedded in the analog video signal. The resulting digitized frame samples are temporarily stored in the frame acquisition buffer and then transferred to system memory.
A digital video source (e.g. a digital camera) provides a digital video signal to the video board via the digital video port. Since the digital video signal already comprises a stream of digitized video frames, the A/D converter (of the video board) is bypassed and frame data is stored directly into the frame acquisition buffer.
The frame acquisition buffer is generally large enough to prevent overrun of data as video data is received, stored, and transmitted to system memory. In some video acquisition boards, the frame acquisition buffer comprises only enough memory sufficient for buffering purposes, such as several Kilobytes. In other types of video acquisition boards, the frame acquisition buffer comprises enough storage for one or more digitized video frames. In these boards, the frame acquisition buffer is generally large enough to store several video frames in order to provide buffering of the bus connection to the host system.
The frame acquisition buffer is generally required to support video data writes by the video source to the buffer and reads of the video data performed by a DMA controller or CPU. One problem that arises is that the digital video image bandwidth varies. When the digital video image bandwidth increases, many times the frame acquisition buffer cannot support the increased bandwidth, and input video data is lost.
Current prior art imaging boards use dual port FIFOs or standard dual-ported memory architectures.
Therefore, an improved system and method is desired for allocating video buffer bandwidth in a video acquisition board. More particularly, an improved system and method is desired which enables the video acquisition board to receive video input data at varying rates, while also providing bandwidth for video data read operations.
SUMMARY OF THE INVENTION
The present invention comprises a video capture system and method which includes adaptive bandwidth allocation in a virtual dual ported frame buffer memory. The video capture system comprises a host computer coupled to a video source, such as a video camera. The host computer includes a CPU, a system memory, a peripheral bus, and a video capture board coupled to the peripheral bus of the computer which receives the video data from the video source. The video source produces a digital video signal which comprises pixel or image data for one or more video images or frames. In the preferred embodiment, the video source comprises a digital camera.
The video capture board comprises an input for receiving digital video data from a video source and a buffer memory coupled to the input which stores the digital video data. The buffer memory preferably comprises a virtual dual ported memory and is preferably a dynamic RAM memory, such as SDRAM. The video capture board also comprises a memory controller coupled to the input and to the buffer memory. The memory controller receives the digital video data from the video source and provides the digital video data to the buffer memory. The video capture board also includes a direct memory access (DMA) controller coupled to the buffer memory and operable to transfer the digital video data from the buffer memory to the computer memory.
In the preferred embodiment, the memory controller comprises a write control block for writing digital video data to the buffer memory, a read control block for reading digital video data from the buffer memory, and refresh logic which controls refresh cycles to the buffer memory. The memory controller further includes arbitration logic which receives requests from each of the write control logic, refresh logic, and the read control logic and grants buffer memory access to one of the write control logic, refresh logic, or the read control logic. The arbitration logic is operable to monitor requests from each of the write control logic, refresh logic, and the read control logic and dynamically allocate bandwidth to the write control logic, refresh logic and the read control logic based on the requests. In the preferred embodiment, write requests and refresh requests are considered high priority requests, and read requests are considered low priority requests.
In the preferred embodiment, the arbitration logic determines if any write requests, refresh requests or read requests are pending. The arbitration logic grants buffer memory access to the write control logic or the refresh logic if a write request or refresh request, respectively, is pending and a read request is not pending. The arbitration logic grants buffer memory access to the read control logic if a read request is pending and a write request or refresh request is not pending. If a high priority request, i.e., either a write or refresh request, and a read request are pending, the arbitration logic determines if the high priority request can be safely delayed. If the high priority request can be safely delayed, the arbitration logic grants buffer memory access to the read control logic. If the high priority request cannot be safely delayed, the arbitration logic grants buffer memory access to the high priority request.
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Butler Cary Paul
Odom B. Keith
Schroeder Charles G.
Schultz Kevin L.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
National Instruments Corporation
Tung Kee M.
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