Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-01
2005-11-01
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S134000, C711S135000, C711S145000
Reexamination Certificate
active
06961827
ABSTRACT:
The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.
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Aneshansley Nicholas E.
Phelps Andrew E.
Shanahan Patricia
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Nguyen T
Sun Microsystems Inc.
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