Via recess in underlying conductive line

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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Details

C257S751000, C257S760000, C257SE23145

Reexamination Certificate

active

10823159

ABSTRACT:
A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

REFERENCES:
patent: 6008114 (1999-12-01), Li
patent: 6436824 (2002-08-01), Chooi et al.
patent: 6613664 (2003-09-01), Barth et al.
patent: 2003/0089992 (2003-05-01), Rathi et al.
patent: 2003/0153198 (2003-08-01), Conti et al.
patent: 2005/0080286 (2005-04-01), Wang et al.

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