Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-07-26
2002-11-19
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C361S780000, C361S792000
Reexamination Certificate
active
06483045
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89101955, filed Feb. 3, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a via-plug layout structure for connecting different metallic layers. More particularly, the present invention relates to a method of connecting different metallic layers by arranging a plurality of empty bars and a plurality of via plugs at fan-shaped positions so that the most stressful location due to electromigration can be determined.
2. Description of the Related Art
Following recent advances in semiconductor manufacturing technologies, devices having deep submicron dimensions can now be fabricated. As the level of integration continue to increase, there is insufficient surface area to accommodate all the interconnecting lines. Hence, more than one layer of interconnects, known as multilevel interconnects design, are often needed in very large-scale integrated (VLSI) circuits. In addition, some of the metallic layers need to be connected. To interconnect metallic layers at different levels, a via hole is formed in the intervening dielectric layer and conductive material is deposited inside the via hole.
At present, most devices in a VLSI circuit are interconnected using more than one interconnect metallic layer. The purpose of having multiple interconnects is to form a wiring line structure that can accommodate the connections due to an increase in device density. In deep submicron integrated circuits, since the level of integration is increased, production yield and reliability of interconnects may deteriorate.
Due to the increase in the level of integration for integrated circuits, dimension of interconnects and via plug or metallic plug is reduced correspondingly. Therefore, area of contact between via plug and interconnect is also reduced. Area of contact is further reduced if there is any misalignment in the process of forming the via plug by photolithographic and etching operation. When area of contact between the via plug and the interconnect is greatly reduced, electric current flowing through the area results in a very high local current density. Localized high current density may lead to electromigration (EM), and an open circuit may result if electromigration persists. Electromigration (EM) occurs when the internal metallic crystals inside a conductive wire are bombarded by too many electrons so that originally bonded crystals are forced to separate. Once electromigration occurs inside a conductive line, reliability of the electronic product is likely to deteriorate.
FIG. 1
is a schematic top view showing a conventional method of laying via plugs to connect different metallic layers.
As shown in
FIG. 1
, labels
100
a
-
100
c
represent sections of a first metallic layer while labels
102
a
and
102
b
represent sections of a second metallic layer, and labels
104
a
-
104
d
represent four via plugs. The via plugs
104
a
-
104
d
electrically connect different sections of the first metallic layer
100
a
-
100
c
with different sections of the second metallic layer
102
a
and
102
b.
For example, the via plug
104
a
electrically connects section
100
a
of the first metallic layer
100
a
with section
102
a
of the second metallic layer.
If a current flows in from section
100
a
of the first metallic layer, a current stress is created. The current passes through via plug
104
a,
section
102
a,
via plug
104
b
and finally into section
100
b
of the first metallic layer. The electric current may continue to flow into via plug
104
c,
section
102
b
of the second metallic layer and via plug
104
d,
and finally reach section
100
c
of the first metallic layer.
The via plugs
104
a
104
d
are connected one-by-one. Therefore, an incoming current flows through each via plug in sequence. Any via plug that has an overly high resistance so as to fail is unlikely to be discovered in an electromigration (EM) test. Hence, it is very difficult to assess the reliability of various via plugs
104
a
-
104
d
by performing an electromigration test using the conventional via plug configuration as shown in FIG.
1
.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a via plug layout structure for via plugs that links different metallic layers and is capable of finding the failed via plug in an electromigration test.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a via plug layout structure for via plugs that links different metallic layers. The via plug layout structure includes a first metallic layer, a second metallic layer, a third metallic layer, a dielectric layer, a first via plug, a plurality of second via plugs and a plurality of empty bars. The dielectric layer is formed over the first and third metallic layer. The first via plug is formed through the dielectric layer to electrically connect to the first metallic layer. The second metallic layer is formed over the dielectric layer and is electrically connected to the first via plug. The plurality of second via plugs are arranged in a fan-shaped pattern through the dielectric layer. The second via plugs are electrically connected to the second metallic layer. Each second via plug is at an identical distance away from the first via plug. The third metallic layer is electrically connected to the second via plugs. The empty bars are positioned in an upper surface of the second metallic layer between the first via plug and the plurality of second via plugs. The empty bars are used to divert incoming current. The number of empty bars employed is preferably the same as the number of second via plugs. Moreover, each empty bar is preferably positioned at the same distance from both the first via plug and the second via plug so that more accurate electromigration tests can be conducted.
Generally speaking, the first metallic layer, the second metallic layer, the first via plug and a second plug are taken as an example. Then empty bars are positioned above the first metallic layer. The first via plug is a single structure and the second via plugs are a fan-shaped pattern. The size of the first via plug is varied to a size, for example, 20% of a via plug size. The electromigraion affected by a process deviation can be observed. The fail via plug can be determined using the combination of voltage contrast, optical microscoped, and conductivity measurement.
The via plug layout structure for connecting different metallic layers in this invention includes a plurality of via plugs arranged into a fan-shaped pattern. The structure further includes a plurality of empty bars positioned between a single via plug and each fanned-out via plug so that current is equally distributed among each of the fanned-out via plugs. Since stress current resulting from current flowing from the single via plug to each of the fanned-out via plug is identical, location where electromigration is most serious can be determined more accurately. Furthermore, single via plugs having different critical dimensions can be fabricated so that the ultimate critical dimension sustainable by the via plug can be obtained after an electromigration test.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 3760302 (1973-09-01), Cohn
patent: 4628406 (1986-12-01), Smith et al.
patent: 4965702 (1990-10-01), Lott et al.
patent: 5012047 (1991-04-01), Dohya
patent: 6239669 (2001-05-01), Koriyama et al.
patent: 6271483 (2001-08-01), Horiuchi et al.
Huang-Lu Shiang
Kao Shih-Chieh
Liu Yuan-Chang
Wang Mu-Chun
Alcala José H.
Cuneo Kamand
United Microelectronics Corp.
Wu Charles C.H.
Wu & Cheung, LLP
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