Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-05-15
2007-05-15
Fourson, George R. (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S702000, C438S703000, C438S709000, C438S761000, C438S778000
Reexamination Certificate
active
11039043
ABSTRACT:
Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.
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Fu Chien Chung
Hsieh Ming-Hong
Huang Yi-Chen
Ouyang Hui
Su Yi-Nien
Fourson George R.
Garcia Joannie Adelle
Taiwan Semiconductor Manufacturing Company
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