Via gouged interconnect structure and method of fabricating...

Details Via gouged interconnect structure and method of fabricating... Via gouged interconnect structure and method of fabricating...

2011-06-21

2011-06-21

Lee, Hsien-ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S758000, C257S774000, C257SE21579, C257SE21584, C257SE21585, C438S627000, C438S629000, C438S643000, C438S653000, C438S687000

Reexamination Certificate

active

07964966

ABSTRACT:
An interconnect structure including a gouging feature at the bottom of a via opening and a method of forming the same are provided. The method of the present invention does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature.

REFERENCES:
patent: 7528066 (2009-05-01), Yang et al.
patent: 7846834 (2010-12-01), Yang et al.
patent: 2008/0067680 (2008-03-01), Sakai et al.
patent: 2008/0128907 (2008-06-01), Yang et al.
patent: 2009/0218691 (2009-09-01), Yang et al.

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