Via formation using oxide reduction of underlying copper

Details Via formation using oxide reduction of underlying copper Via formation using oxide reduction of underlying copper

1998-12-11

2001-04-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S627000, C438S660000

Reexamination Certificate

active

06218303

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit manufacture and, more particularly, to a method for removing oxide from exposed regions of a conductor pattern. A major objective of the invention is to provide for improved oxide removal of copper conductors exposed through via apertures in manufacturing technologies with features sizes below 0.2 microns.
Much of modern progress is associated with the increasing prevalence of microprocessor-based systems, which has been made possible in part by advances in integrated circuit manufacturing technology. These advances have permitted ever-smaller circuit features to be defined so that more circuit elements can be formed per unit area. This increased circuit density has permitted greater functionality per integrated circuit. Also, since circuit elements are closer together, the speed at which they can communicate is increased. Also, the smaller devices tend to consume less power, so the net result is greater functionality and speed with reduced power consumption.
While there is considerable variety in integrated circuits, a typical integrated circuit comprises a semiconductor substrate in which active circuit elements are defined by patterned doping and an overlaying interconnect structure of plural patterned metal layers insulated from each other and from the substrate by dielectric layers. Connections to the substrate and between metal layers are typically achieved using metal vias that extend through the dielectric material. The prevalent semiconductor material is silicon, the prevalent interconnect metal is aluminum, and the prevalent dielectric material is silicon dioxide. Each of these materials is relatively easy to work with and pattern. Collectively, they work well together in that small amounts of contamination by any of these materials migrating into others is not a major problem for the finished device.
However, as the integrated circuit features shrink with advancing technology, the resistance of the smaller-cross-section aluminum conductors increases, resulting in poor electrical performance and relatively high heat generation. This has led generally to a trend to forsake aluminum in favor of copper to take advantage of the latter's greater conductivity. Copper is harder to pattern than aluminum, but a damascene process has been developed that permits the required patterning.
Another problem with copper is that it is a poison in the context of integrated circuits in the sense that active semiconductor regions can be impaired by the presence of copper. Unless appropriate countermeasures are taken, copper atoms can migrate from the conductors to the semiconductor substrate. This migration can cause an integrated circuit to deteriorate over time-possibly leading to eventual failure. Thus, the use of copper can raise concerns for reliability. This reliability issue is addressed by encasing the copper conductors in barrier materials, e.g., tantalum, to prevent migration of copper atoms.
For example, silicon dioxide dielectric is deposited over a copper pattern. Apertures can be photolithographically defined where vias are to be formed. The apertures expose copper that is to be covered with barrier metal. However, before the barrier metal can be deposited it is necessary to remove any oxidization of the copper to ensure a good metal-to-metal electrical contact.
A comparable situation exists when aluminum conductors are involved since contaminants must be removed from aluminum exposed through via apertures before via metal is deposited. The aluminum is typically cleaned by sputtering through via apertures using a process analogous to sandblasting. However, sputtering when copper is involved can result in copper being embedded in the oxide sidewalls of the vias. These copper atoms escape coverage by the subsequently deposited barrier metal, and thus are a threat to device reliability as they are free to migrate to the active semiconductor regions. In addition, it is difficult to sputter effectively through the high-aspect-ratios apertures associated with smaller feature dimensions. So the sputter method used for cleaning aluminum through apertures does not translate well to copper-based integrated-circuit manufacture. Accordingly, what is needed is a better integrated-circuit manufacturing method that provides for removing oxidation from copper exposed through via apertures.
SUMMARY OF THE INVENTION
The present invention provides for removing copper oxide using a gaseous reducing agent. More specifically, the method involves forming a patterned metal layer including copper, forming a dielectric over the metal layer with via apertures exposing some of the copper, exposing the copper to a gaseous reducing agent, and then depositing barrier metal in the aperture. Preferably the reduction reaction is a two-step reaction, yielding Cu
2
O as an intermediate product. The reaction can be conducted at a temperature above 300° C., preferably between 350° C. and 450° C. Exemplary reducing agents are carbon monoxide and hydrogen.
To minimize the opportunities for re-oxidation of the copper prior to deposition of barrier metal, the integrated circuit can be transferred by a robotics system from a reduction chamber to a barrier-metal deposition chamber within a cluster that maintains a high vacuum (less than 10
−8
Torr) in the transfer environment enclosing the two chambers.
After transfer, a barrier metal is deposited over the exposed copper, coating the via apertures, as well as trenches formed according to the preferred damascene process for patterning copper. A seed layer of copper can then be deposited in preparation for bulk electroplating of the copper. Chemical-mechanical polishing can be used to remove metal except within the trenches and vias.
The reduction reaction is far gentler mechanically than is the sputtering process used to clean aluminum. Accordingly, there is less chance for metal atoms to be lodged into via sidewalls, from where they could migrate to the active regions of the semiconductor material. Thus, the invention provides an improvement in reliability relative to similar devices manufactured using sputtering to remove copper oxide. In addition, the high-aspect-ratio via apertures associated with decreasing feature dimensions interfere less with a reduction reaction than a sputtering process. These and other features and advantages of the invention are apparent from the description below with reference to the following drawings.


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