Via formation for multilayered metalization

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156644, 156646, 156652, 156655, 1566591, 156667, 156668, 20419232, 357 71, 427 90, B44C 122, C23F 102, C03C 1500, B29C 3700

Patent

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046594272

ABSTRACT:
A process for enhanced formation of vias in multilevel conductive structures for integrated circuit devices. A semiconductor wafer, bearing a multilayered first level metalization characterized by a tungsten alloy top layer, is annealed in a suitable ambient so as to form a distinctly colored superficial film atop the first level metalization. The interlevel dielectric is then deposited and subsequently selectively dry etched until the film becomes discernible, the film itself serving as an etch stop so as to protect the top layer of the first level metalization. Exposed portions of the superficial film are then removed through a standard plasma etch step. Remaining areas of the film promote intimate binding between the first level metalization and the interlevel dielectric.

REFERENCES:
patent: 3900944 (1975-08-01), Fuller et al.
patent: 4184909 (1980-01-01), Chang et al.

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