Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-10-10
2006-10-10
Smith, Matthew (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S704000, C438S705000, C438S723000, C438S724000, C438S725000, C438S740000, C438S743000, C438S744000, C438S751000, C438S756000, C438S757000, C257SE21579
Reexamination Certificate
active
07119006
ABSTRACT:
A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32). Simultaneous etching of the trench through intermetal dielectric layer (30), stopping on the trench etch stop layer (28) if present, simultaneously with the etching of the remainder of the via through the interlevel dielectric layer (26) that stops on the via etch stop layer (24), is then performed. After clearing the via etch stop layer (24) from the via bottom, a copper conductor (40) is then formed into the trench and via, for example by electroplating and planarization by chemical mechanical polishing over a barrier layer (41).
REFERENCES:
patent: 5741626 (1998-04-01), Jain et al.
patent: 6054384 (2000-04-01), Wang et al.
patent: 6127258 (2000-10-01), Watanabe et al.
patent: 6362093 (2002-03-01), Jang et al.
patent: 6380096 (2002-04-01), Hung et al.
patent: 6410426 (2002-06-01), Xing et al.
patent: 6448176 (2002-09-01), Grill et al.
patent: 6465340 (2002-10-01), Wang et al.
patent: 6583047 (2003-06-01), Daniels et al.
patent: 2002/0187627 (2002-12-01), Yuang
patent: 2003/0040172 (2003-02-01), Brennan
Brady III Wade James
Garner Jacqueline J.
Pham Thanh V.
Smith Matthew
Telecky , Jr. Frederick J.
LandOfFree
Via formation for damascene metal conductors in an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Via formation for damascene metal conductors in an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Via formation for damascene metal conductors in an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3628422