Via-first dual damascene process

Details Via-first dual damascene process Via-first dual damascene process

2003-08-15

2004-08-24

Gurley, Lynne (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S666000, C438S780000, C438S782000

Reexamination Certificate

active

06780761

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates generally to copper interconnects. More particularly, the present invention relates to a via-first dual damascene process capable solving DUV photoresist residue in an isolated via recess during the trench patterning.
2. Description of the Prior Art
Damascene processes incorporated with copper interconnect technique are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. The copper damascene processes provide a solution to form a conductive wire coupled with an integral via plug without the need of dry etching copper. Either a single damascene or a dual damascene structure is used to connect devices and/or wires of an integrated circuit. Typically, the dual damascene process encompasses trench-first, via-first, partial-via, and self-aligned processes, in which the via-first dual damascene process comprises first defining a via opening in dielectrics and then defining a trench above the via opening by using several lithographic and etching steps.
Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are cross-sectional schematic diagrams showing several typical intermediate phases of a semiconductor wafer during the via-first dual damascene process according to the prior art method. As shown in
FIG. 1
, a semiconductor substrate
100
is provided. A conductive structure
111
and conductive structure
112
such as damascened copper wirings are provided in a device layer
101
of the semiconductor substrate
100
. Subsequently, a capping layer
115
such as silicon nitride is deposited to cover the exposed conductive structures
111
and
112
, and the device layer
101
over the semiconductor substrate
100
. A stacked dielectric layer
120
is formed on the capping layer
115
. The stacked dielectric layer
120
is typically composed of a first dielectric layer
121
, a second dielectric layer
123
, and an etch-stop layer
122
interposed between the first dielectric layer
121
and the second dielectric layer
123
. A silicon oxy-nitride layer
130
is then deposited on the first dielectric layer
121
. Thereafter, a first DUV photoresist layer
140
having via openings
141
and
142
is formed on the silicon oxy-nitride layer
130
, assuming that the via opening
141
is an isolated via pattern, i.e. there is no other via opening located in the proximity of the via opening
141
, and the via opening
142
is a dense via pattern. Using the first DUV photoresist layer
140
as a etching mask, an etching process is performed to etch away, in the order of, the silicon oxy-nitride layer
130
, the stacked layer
120
, to the capping layer
115
, through the via openings
141
and
142
, thereby forming deep via holes
151
and
152
.
As shown in
FIG. 2
, after stripping the first DUV photoresist layer
140
off the silicon oxy-nitride layer
130
, a gap-filling polymer (GFP) layer
201
is coated on the semiconductor substrate
100
and fills the via holes
151
and
152
. The GFP layer
201
is typically composed of an i-line resist known in the art. Coating of the GFP layer
201
is known in the art and optional post-baking step may be carried out if desired. As shown in
FIG. 3
, the GFP layer
201
is then etched back to a predetermined depth, such that the exposed surface of the GFP layer
201
is lower than the surface of the silicon oxy-nitride layer
130
, thereby forming recesses
301
and
302
. As shown in
FIG. 4
, a second DUV photoresist layer
401
is coated on the semiconductor substrate
100
and fills the recesses
301
and
302
using spin coating method known in the art.
Please refer to
FIG. 6
with respect to
FIG. 5
, where
FIG. 5
is a cross sectional view of
FIG. 6
along line AA″,
FIG. 6
is a top view of FIG.
5
. Following the coating of the second DUV photoresist layer
401
, a lithographic process is carried out. In the lithographic process (or trench photo-lithographic process), a mask (not shown) having a predetermined trench pattern thereon is provided as a photo-mask, which is positioned over the semiconductor substrate
100
. Light such as deep UV is projected on the photo-mask and passes through clear areas of the photo-mask to irradiate the underlying second DUV photoresist layer
401
, thereby forming latent trench images (not shown), which is soluble in a developer, over the respective recesses
301
and
302
in the second DUV photoresist layer
401
. Thereafter, the exposed second DUV photoresist layer
401
is developed using a proper developer that is usually hydrophilic. The latent trench images are removed to form trenches
411
and
412
over the recesses
301
and
302
, respectively.
As best seen in
FIG. 5
, however, DUV photoresist residues
511
are observed at the bottom of the recess
301
(some might be left on the sidewalls of the recess
301
) over the isolated via hole
151
after the development of the second DUV photoresist layer
401
. The DUV photoresist residue
511
results in undesired micro-trenching effects or fences in the isolated via hole
151
, which affect the performance of the integrated circuit. The phenomenon of the DUV photoresist residue
511
might be caused due to the fact that the upper surface of the GFP layer
201
is a hydrophobic surface, while the developer is hydrophilic solution. Further, capillarity deteriorates the DUV photoresist residue phenomenon during the development of the second DUV photoresist layer
401
.
SUMMARY OF INVENTION
Accordingly, the primary object of the present invention is to provide an improved dual damascene process to alleviate or eliminate DUV residue in the isolated via at the scale of deep sub-micron, thereby avoiding the above-mentioned micro-trenching or fence effects.
To achieve the above object, a via-first dual damascene process is provided.
The via-first dual damascene process includes the following steps:
providing a semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate, wherein the dielectric layer has a via opening exposing the conductive structure;
filling the via opening with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer;etching the GFP layer back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening; and
performing a surface treatment for altering surface property of the sidewalls and the exposed surface of the GFP layer, thereby preventing a subsequent deep UV photoresist from interacting with the sidewalls or the exposed surface of the GFP layer either in a chemical or physical way.
In accordance with the present invention, an improved via-first dual damascene process is provided. The via-first dual damascene process includes the following steps:
providing a semiconductor substrate having a conductive structure and a dielectric layer on the semiconductor substrate, wherein the dielectric layer has a via opening exposing the conductive structure;
filling the via opening with a gap-filling polymer to form a gap-filling polymer (GFP) layer on the dielectric layer;
etching the GFP layer back to a predetermined depth such that an exposed surface of the GFP layer is lower than surface of the dielectric layer to form a recess, thereby exposing portions of sidewalls of the via opening;
performing a surface treatment for unifying surface condition of the sidewalls and the exposed surface of the GFP layer;
filling the recess with a deep UV (DUV) photoresist to form a DUV photoresist layer on the dielectric layer;
performing a lithographic process to form a trench opening in the DUV photoresist layer above the via opening; and
etching the dielectric layer and the GFP layer through the trench opening using the DUV photoresist layer as an etching mask.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the follow

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