Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-11-13
2003-02-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C427S523000, C252S079200, C205S087000, C205S167000
Reexamination Certificate
active
06518182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a via-filling process. More particularly, the present invention relates to a via-filling process for filling metals into minute pores such as blind holes provided in the substrate of printed circuit boards and the like.
2. Description of the Background Art
Recently, a build-up method is applied to mounting circuits for electronic equipment such as cellular phones, personal computers, videos, game machines, and the like. In the build-up method, small holes such as through-holes and via-holes are provided in a laminated board, and metals are deposited in such small holes to allow interconnection among several different circuit layers. Of these small holes, via-holes which are minute blind holes are plated with metals (via-hole plating) or filled with metals (via-filling) for interconnecting the layers.
With via-hole plating, in which a metal film is formed on the side or bottom in side the via-holes, there are difficulties in layering a conductive layer over the holes. In addition, the area of metal film deposition must be increased to guarantee conductivity in the interconnection. On the other hand, the via-filling process in which metals are filled into via-holes can completely fill the holes with the metals and allow the other holes to be formed on these holes if these are flat after via-filling. Therefore, this process is advantageous for downsizing the devices. For this reason, the demand is shifted from the via-hole plating process which is limited to flattening of insulating materials to the via-filling process in which interlayer holes can be filled.
Conventionally, via-filling is performed by activating the conductive layer in the bottom of an insulating layer in which holes are formed, forming pillars or posts by electrolytic copper plating, and flattening the surface by removing deposited copper by grinding. Another method comprises activating only the conductive layer in the bottom by electroless copper plating and selectively piling by electroless copper plating. Of these methods, the former method requires grinding of deposited copper plating layers having a substantial thickness, whereas the latter method has a drawback of requiring a considerable period of time to obtain a copper plating layer with a desired thickness.
Accordingly, an object of the present invention is to provide a process of efficiently performing via-filling by means of a simple procedure.
The present inventors have conducted extensive studies on acid copper plating baths which can efficiently perform via-filling and, as a result, have found that a bath with a high copper sulfate concentration and a low sulfuric acid concentration is suitable for filling in blind via-holes with plating.
Although a typical conventional sulfuric acid copper plating bath for printed circuit boards contains about 75 g/L of copper sulfate and 180 g/L of sulfuric acid, a composition containing about 225 g/L of copper sulfate and about 55 g/L of sulfuric acid which is used for copper plating for ornamental purposes has been found more suitable for filling in blind via-holes.
However, this composition impairs properties of printed circuit boards, such as elongation rate and tensile strength of the copper plating film, or increases fluctuation of the plating thickness, even if additives for printed circuit boards are used.
As a result of extensive studies to remove drawbacks such as impaired properties using this composition, the present inventors have found that an acid copper plating bath having the same properties as the conventional bath for printing circuit boards and exhibiting superior via-filling properties (hole filling) can be obtained by adjusting the proportion of the additives and that copper can be preferentially deposited in via-holes of print-circuit boards and the like using this bath composition.
SUMMARY OF THE INVENTION
Specifically, the present invention provides a via-filling process comprising providing a substrate having blind via-holes, making the substrate electrically conductive, and plating the substrate in an acid copper plating bath which comprises the following components (A) to (E):
(A) copper sulfate at a concentration of 100-300 g/L,
(B) Sulfuric acid at a concentration of 30-150 g/L,
(C) a first component selected from the group consisting of polypropylene glycol, Pluronic surfactants, Tetronic surfactants, polyethylene glycol glyceryl ether, and polyethylene glycol dialkyl ethers at a concentration of 10-1000 mg/L,
(D) a second component selected from the group consisting of sodium sulfoalkyl sulfonates, bis-sulfo organic compounds, and dithiocarbamic acid derivatives at a concentration of 0.1-20 mg/L, and
(E) a third component selected from the group consisting of polyalkylene imines, 1-hydroxyethyl-2-alkyl imidazoline chlorides, auramine and its derivatives, methyl violet and its derivatives, crystal violet and its derivatives, and Janus black and its derivatives at a concentration of 0.05-10 mg/L.
Other objects, features and advantages of the invention will herein after become more readily apparent from the following description.
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patent: 4316778 (1982-02-01), Whitehurst
patent: 4576685 (1986-03-01), Goffredo et al.
patent: 4781801 (1988-11-01), Frisby
patent: 4786746 (1988-11-01), Miljkovic
patent: 5587006 (1996-12-01), Shepherd et al.
Hagiwara Hideki
Ishikawa Masami
Kimizuka Ryoichi
Ebara-Udylite Co., Ltd.
Lee Calvin
Smith Matthew
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