Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-04-23
2003-07-29
Lazarus, Ira S. (Department: 3749)
Metal working
Method of mechanical manufacture
Electrical device making
C029S852000
Reexamination Certificate
active
06598291
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to printed circuit boards and to methods for fabricating printed circuit boards. More particularly, the present invention relates to printed circuit boards with improved vias which provide electrical communication between wiring patterns formed on two opposing surfaces of a circuit board and/or within the internal strata of the circuit board, and to methods for making improved circuit boards having such vias.
BACKGROUND OF THE INVENTION
Increasing levels of integration of integrated circuit (IC) chips reduces the chip count of a functional circuit, while significantly increasing the input/output (I/O) count of the individual integrated circuits making up the functional circuit. This drive for increased circuit and component density in the individual IC chips leads to a parallel drive for increased circuit and component density in the printed circuit boards carrying the chips and in the assemblies using them.
Typically, a conventional printed wiring board carries ICs as well as other discrete electronic components and circuit elements, which are interconnected to provide the particular electronic circuit functions. In the prior art, those ICs, discrete electronic components, and circuit elements are usually bonded to the printed wiring board using vias or through holes formed in the printed wiring board through which lead wires may be inserted and soldered to the board. However, there have been advances in surface mounting technology widely employed in the printed wiring board manufacturing field. This technology permits an IC to be mounted together with its associated elements on the printed wiring board without forming any through holes or vias in the board. Thus, ICs and other on-chip elements may be mounted on a surface mount land or chip land directly without using the through holes or vias.
To provide for the interconnections between the on-chip elements on the surface mount land on one side and a circuit on the opposite side of, or within, the printed wiring board, the appropriate vias are often provided remotely from the surface mount land, and any wiring pattern required for interconnecting the elements by way of the vias must be formed on the surface of the base plate.
Thus, according to the prior art, the surface mount land or chip land and the vias or through holes are provided at different locations on the printed wiring board. As the size of each of the ICs and other elements is reduced, a corresponding reduction in the size of the surface mount land is required so that required board space is minimized. The wiring pattern that includes leads drawn out from the surface mount land and distributed across different locations must be accordingly fine, but technically, this is practically difficult to achieve. It is also difficult to secure the space required for wiring the leads. In particular, for double-sided high-density wiring pattern implementation, this space limitation poses a problem.
The vias formed in the printed wiring board are exposed on each of the opposite sides of the board. When leads are inserted through the corresponding vias, and the associated circuit components are fixed by the board in solder, surplus solder may flow through the vias, thereby reaching the components on the surface mount land.
In other conventional circuit boards which carry wiring patterns formed on two opposing major surfaces, vias or through holes are formed at desired positions after conductive layers are formed on the entire surface of the opposing major surfaces of the circuit board. Inner surfaces of the thus formed vias are coated with plated layers through the use of a chemical plating method or a chemical/electrical plating method, thereby providing electrical communication between the conductive layers formed on the two major surfaces or internal to the circuit board by way of the plated layers.
The vias are formed through the use of a drilling method or a punching method. Therefore, there is the possibility that the circuit board or the conductive layers become distorted during the formation of the through holes. The thus formed distortion will adversely influence the formation of the plated layers so that an effective electrical connection cannot be achieved between the two conductive layers. In addition, fine wiring patterns cannot be formed near the vias due to the distortion of the conductive layers. Thereafter, the conductive layers are shaped in a desired configuration to obtain wiring patterns formed on both of the major surfaces of the circuit board.
Another example of prior art via connectors is disclosed in U.S. Pat. No. 3,601,523 “THROUGH HOLE CONNECTORS” to Arndt, issued on Aug. 24, 1971, wherein a conductive adhesive is disposed in the through holes or vias for providing electrical communication between the conductive layers formed on both of the major surfaces of the circuit board. In the device of the '523 patent, the vias are formed after the conductive layers are formed on both of the major surfaces of the circuit board and, therefore, there is a possibility that the conductive layers will become distorted near the vias. Moreover, in the '523 patent, electrical communication between the conductive layer and the conductive adhesive is achieved only through the use of the thickness of the conductive layer. In addition, the conductive adhesive is exposed to the ambience. Therefore, the shaping of the wiring patterns must be conducted through the use of a dry film or a resist sheet.
The increased circuit and component density in the printed circuit boards makes the ability to locate either solder surface mount components or place additional circuitry layers directly above conductive vias highly desirable. This is especially the case when the density of the vias required to service the I/O's of the surface mount components is such that there is no surface area available for attachment pads interstitial to the through hole grid.
The problem is especially severe with fine pitch ball grid array components and flip chip attach integrated circuits. Soldering of these surface mount components to the surface pads, i.e., lands, of conventional vias is highly undesirable. This is because the solder used for assembly tends to wick down into the vias. The result is low volume, unreliable solder joints.
One solution that has been proposed is filling the vias. However, known methods of filling vias of printed circuit boards have deficiencies. For example, they suffer from bleed of the resin component of the fill material along the surface of the boards. This resin also bleeds into the holes which are not to be filled. This leads to short circuits and to soldering defects during assembly.
Thus, conductive vias provide an immediate connection from a surface mounted device to the core of a printed circuit board, thereby avoiding inefficient fan out routing patterns that consume space on the outer layers of the multilayer board. These designs, however, present significant assembly problems. Small vias act as entrapment sites for materials that can eventually re-deposit onto the host surface mount land and cause both assembly and reliability problems. Also, these vias act as unintended reservoirs for solder paste that is stenciled onto the surface mount land and used to attached an electronic device to the board. Consequently, an allowance must be made of the solder paste that will be captured by the via and will not be available for the solder joint formed between the device and the board. Typically, the same allowance is made for each via by slightly enlarging the solder paste stencil aperture for each surface mount pad containing a via by some common amount. Because the precise allowance needed varies from via to via, this method leads to an insufficient amount of paste for some lands causing poor solder joints and an over-abundance of solder on others causing solder shorts; both of which unfavorably impact assembly yields.
Another example of prior art via connectors is disclosed in U.S. Pat.
Miscikowski Pamela L.
Parker, Jr. John L.
Lazarus Ira S.
Rinehart K. B.
Viasystems, Inc.
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