Via alignment, etch completion, and critical dimension measureme

Details Via alignment, etch completion, and critical dimension measureme Via alignment, etch completion, and critical dimension measureme

1998-10-05

2000-12-19

Tran, Andrew

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Optical characteristic sensed

438 10, 438401, 438975, H01L 2100

Patent

active

061626503

ABSTRACT:
A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.

REFERENCES:
patent: 4642672 (1987-02-01), Kitakata
patent: 5736863 (1998-04-01), Liu
patent: 5780870 (1998-07-01), Maeda et al.
patent: 5998226 (1999-12-01), Chan
patent: 6008060 (1999-12-01), Chang et al.

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