Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2001-11-03
2003-10-28
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S154000, C365S189070, C365S207000
Reexamination Certificate
active
06639866
ABSTRACT:
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable]
BACKGROUND OF THE INVENTION
One embodiment of the present invention relates to static memories or multi-port register files. More specifically, one embodiment of the present invention relates to very small swing high performance asynchronous CMOS static memory having a column multiplexing scheme.
Currently, memories or register files are widely used in numerous applications in various industries. Although, typically it is desirable to incorporate as many memory cells as possible into a given area, some known memories or register files are often perceived as physically too large (i.e., they take up too much silicon area) and/or are too slow for a given product definition. In addition, power dissipation is another parameter that all memory designers are forced to consider in order to make a product cost effective. Additionally, some applications demand that such memories or register files function synchronously or asynchronously.
One type of basic storage memory or register file is the CMOS static random access memory (alternatively referred to as the “SRAM”), which retains its memory state without refreshing as long as power is supplied to the cell. In one embodiment of a SRAM, the memory state is usually stored as a voltage differential within a bistable functional element such as an inverter loop. However, some currently known SRAM memories don't work in conjunction with low supply voltages. That is, as the supply voltage approaches about 1.0 volt or less, the access time increases exponentially. Moreover, such currently known SRAM memories are susceptible to noise. That is noise may be present, on a bitline for example, and may false trip one or more associated devices such as sense amplifiers.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
Features of the present invention may be found in a high performance CMOS static memory. In one embodiment, the present invention may be found in a differential high speed CMOS static memory that operates synchronously or asynchronously with a low power supply voltage. In this embodiment, the CMOS static memory has a read access time of about 3 nanoseconds or less, and is more robust than currently known static memories, eliminating noise effects that may falsely trip a sense amplifier used with the static memory.
One embodiment of the present invention relates to a multi-port register file memory adapted to be used in applications where a power supply of less than about 1.08 volts occurs. In this embodiment, the memory includes at least one memory cell, a differential sensing device coupled to a voltage reference device and adapted to sense a small voltage swing. This embodiment also includes a latched output circuit coupled to the differential sensing device.
In another embodiment, the register file memory relates to a multi-port register file memory adapted to be used in applications where a power supply of less than about 1.08 volts occurs. In this embodiment, the memory comprises a plurality of memory cells arranged in a plurality of rows and columns. The memory further includes at least one read port and one write port coupled to each of the storage elements. A differential sensing device is included which is adapted to sense a small voltage swing. This device also includes a voltage reference and latched output circuit which are coupled to the differential sensing device.
In yet another embodiment, the present invention relates to a multi-port register file memory, where the memory includes a plurality of memory cells arranged in rows and columns, a means for selecting one or more of the memory cells, and a means for sensing a small bitline voltage swing.
Yet another embodiment of the present invention relates to a method for improving speed and increasing performance in a multi-port register file memory having a plurality of storage elements. In this embodiment, the method includes selecting at least one of the memory cells, and differentially sensing a small voltage swing.
Yet still another embodiment of the present invention relates to a method for reading data stored in a multi-port register file memory having a plurality of memory cells arranged in rows and columns. This embodiment includes selecting one of the memory cells, flowing a current through at least one read transistor pair of a memory cell in one (or possibly more) column(s), causing an output (of a sense amplifier connected to at least one column) to switch accessed data to full CMOS logic levels.
Other aspects, advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings, wherein like numerals refer to like parts.
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Buer Myron
Knebelsberger David W.
Slamowitz Mark
Smith Douglas D.
Broadcom Corporation
McAndrews Held & Malloy Ltd.
Nguyen Tan T.
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