Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-09-09
2004-07-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000, C326S086000, C326S047000
Reexamination Certificate
active
06765409
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
The present application claims benefit of the filing date of U.S. provisional application No. 60/322,255, filed on Sep. 13, 2001, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits (IC) containing programmable logic, and more particularly to a programmable interconnect structure for use in such ICs.
Advances in semiconductor fabrication processes which have enabled an ever increasing number of transistors to be formed on an IC fabricated on a single semiconductor substrate, and have seen a parallel increase in the type and number of functions that such ICs may perform. One class of ICs, commonly referred to as programmable logic devices (PLD), enables its users to program the functions that the PLD is to perform. The various hardware blocks, commonly known as logic blocks, in a PLD are typically not electrically connected to one another when the PLD is first supplied by its manufacturer. The user must first program the PLD to carry out the functions specified by the user. Programming of a PLD is usually performed with the aid of software in which the interconnections between various logic blocks are first specified, either by means of a table or a list of Boolean functions. After being executed, the software causes the specified interconnections to occur, in other words, it programs the PLD to create the desired logic and interconnections. A PLD thus eliminates the need for design-intensive and time-consuming efforts required for custom-specific ICs
A PLD usually includes arrays of logic cells, known as logic blocks, that are programmable and are selectively connected to arrays of interconnect lines to attain both combinatorial as well as sequential logic functions. Programming of programmable logic blocks, as well as their connections to the selected lines (e.g., bus lines), is typically achieved by establishing the states of a multitude of programmable elements, such as memory cells or fuses, disposed in the PLD. The logic blocks disposed in a PLD often arc divided into arrays of AND and OR functions, adapted to perform the specified functions.
One type of PLD is programmable array logic (PAL). In a PAL, the AND arrays are programmable, while the OR arrays are fixed. Accordingly, in a PAL, the AND gates are programmed to provide the product term logic signals which are subsequently summed by the OR gates.
Another type of PLD is known as programmable logic array (PLA) in which both the AND and OR arrays are programmable. In a PLA, the product terms in the AND array may be shared by the OR array to provide the specified logic functions. Both PALs and PLAs often include flip-flops, in addition to the AND and OR arrays, to provide sequential logic operations.
A disadvantage of both PALs and PLAs is their logic utilization. In other words, after being configured, some of the logic blocks disposed within a PLD may remain unutilized. To increase their utilization, PLDs have been adapted to include one or more macro cells. A macro cell is a logic block or a group of logic blocks that may be configured to perform many different and relatively more complex logic functions. A macro cell may be selectively interconnected to other macro cells or logic blocks. Macro cells enable attainment of a more granular structure and, therefore, increase the utilization of the semiconductor surface area in which the PLD is formed and, therefore, reduce cost.
Another type of IC which integrates a number of macro cells, analog and/or memory blocks on the same silicon substrate is commonly referred to as system-on-chip (SoC). An SoC may be configured to perform functions that would otherwise require several different ICs to perform.
The macro cells disposed in a conventional SoC are typically either hard wired during the fabrication process or are later programmed (i.e., configured) following the fabrication process. If hardwired during the fabrication process, an SoC may not be reconfigured following the completion of the fabrication process. If not configured during the fabrication process, an SoC is often configured with the aid of software. Such configuration software may be subsequently used to reconfigure the SoC to enable it to perform functions that are different from those for which the SoC was configured before. A reconfigurable SoC often employs arrays of interconnects which are selectively coupled to one another to provide the specified logic functions.
FIG. 2 of U.S. Pat. No. 5,504,440, issued to Sasaki, illustrates an interconnection between a logic cell 20 and input and output buses 23 and 17. Each line of bus 12 is shown as being coupled to an input terminal of logic cell 20 via “a programmable three state buffer operating under control of an input signal supplied to it on line 54. Line 54 is coupled to a register or other means within which the program for controlling the overall programmable logic device is stored.”
As disclosed in Sasaki, “A separate bit in this register, memory, a fuse or other means, is used to control a corresponding one of the programmable connections in the drawing in FIG. 2. Other bits are used to control other programmable connections elsewhere in the programmable logic device. Thus the control memory typically will have as many bits stored therein as there are programmable connections to be controlled. Of course, where two configurations are mutually exclusive and one, and only one, is always provided, the complementary state of a single bit can control two configurations. Under control of the memory bit, circuit 52
a
is either active or in a high impedance state. When the input 54
a
is enabled, circuit 52
a
repeats the signal coupled to its input node 57
a
. In other words, if a logical 1 is present on conductor 12
a
of bus 12, then input node 57
a
of driver 52
a
will be a logical 1. Assuming that control line 54
a
is enabled, then the output from driver 52
a
will also be a logical 1. Of course, the same conditions apply if a logical 0 is present on conductor 12
a
. Each of the drivers 52 functions in the same manner. On the other hand, if control line 54 is not enabled, then the driver circuits present a high impedance state and functionally behave as an open circuit. In other words, node 55 is completely disconnected from bus 12. This allows an input node 41 to be disconnected from the bus 12 when that input node is not to receive signals from bus 12.”
FIG. 9A of U.S. Pat. No. 4,870,302, issued to Freeman, is the schematic of a circuit for making a number of different interconnections. “Thus, in FIG. 9A, pass transistor 2, when activated into the conducting state, connects lead 90-3 to lead 90-1. Pass transistor 1, when conducting, connects lead 90-3 to lead 90-4. Pass transistor 4, when conducting, connects lead 90-4 to lead 90-2 and pass transistor 3, when conducting, connects lead 90-1 to lead 90-2. Pass transistors 6 and 5, when off, separate lead 90-2 from lead 90-3 and separate lead 90-1 from lead 90-4 respectively. Thus, should it be desired to connect vertical lead 90-2 to vertical lead 90-3, pass transistor 6 is activated. Likewise, should it be desired to connect horizontal lead 90-1 to horizontal lead 90-4, pass transistor 5 is activated.”
Conventional interconnect structures of the types that are deployed in known PLDs or SoCs may limit the reconfigurability of the macro cells disposed therein and may also limit the speed of operation. Such problems are further compounded as the supply voltages continue to scale down.
BRIEF SUMMARY OF THE INVENTION
A programmable interconnect structure (hereinafter referred to as connector), in accordance with the present invention, includes two separate paths. Disposed within the first path are first and second CMOS transmission gates (hereinafter referred to as transmission gates) and a first buffer. Disposed within the second path are third and fourth transmission gates and a second buffer. A first terminal of the first transmission gate is coupled to a first termina
Bobra Yogendra
Vora Madhu
Extensil Corporation
Tokar Michael
Tran Anh Q.
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