Very low overhead shared resource boundary scan design

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371 225, 324765, G01R 3128

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057152543

ABSTRACT:
An output boundary scan cell includes an output buffer structure (51) connected between a shared capture/shift memory (17) and an output terminal. The output buffer structure is responsive to initiation of a test mode of operation for latching at the output terminal functional test data from the shared capture/shift memory and for isolating the output terminal from test data subsequently stored in the shared capture/shift memory during the test mode of operation.

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David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.

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