Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2006-05-02
2006-05-02
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000
Reexamination Certificate
active
07039790
ABSTRACT:
A data processing system with a microprocessor. The microprocessor has an instruction execution pipeline including fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execute packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. A predetermined bit in each instruction marks whether the next instruction is executed in parallel with the current instruction. Instructions in an execute packet are dispatched to appropriate functional execution units based on instruction type. Upon a branch into an execute packet instructions at memory addresses before the branch location are not executed in parallel with instructions following the branch location.
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IBM: Journal of Research and Development—The IBM RISC System/6000 Processor, vol. 34, No. 1, pp. 12-21, 37-43; and 85.
Brown Richard A.
Simar, Jr. Laurence R.
Brady III W. James
Ellis Richard L.
Huisman David J.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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