Very large scale integrated planar read only memory

Details Very large scale integrated planar read only memory Very large scale integrated planar read only memory

1995-04-21

1997-01-21

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365206, 365203, 326 94, G11C 800

Patent

active

055965440

ABSTRACT:
Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

REFERENCES:
patent: 5003513 (1991-03-01), Porter et al.
patent: 5124584 (1992-06-01), McClure
patent: 5305283 (1994-04-01), Shimokura et al.

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