Very fast pipelined shifter element with parity prediction

Details Very fast pipelined shifter element with parity prediction Very fast pipelined shifter element with parity prediction

1997-07-14

1999-11-02

Chung, Phung M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

714799, 714800, G06F 1110

Patent

active

059789573

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The invention relates to shifting of an operand in a shifting unit.


PRIOR ART

A shift register, or shift unit, has the ability to transfer information in a lateral direction. Shift registers normally represent n-stage devices whose output consist of an n-bit parallel data word. Application of a single clock cycle to the shift register device causes the output word to be shifted by one bit position from right to left (or from left to right). The leftmost (or rightmost) bit is lost from the "end" of the register while the rightmost (or leftmost) bit position is loaded from a serial input terminal.
Shift registers with parallel outputs, and with combinational logic fed from those outputs, are of great importance in digital signal processing, and in the encoding and decoding of error-correcting and error-detecting codes. Such registers may be implemented in hardware or in software, and may be binary or q-ary. (Hardware implementation is usually convenient only for binary and sometimes ternary logic.)
Shift units are commonly used together with arithmetical and logical units. FIG. 1 shows a block diagram of a prior art execution unit comprising a shift unit together with an arithmetical and a logical unit. All those units generally have to match in speed in order to avoid having unbalanced net length and signal propagation time. However, particularly the shift unit appears to be critical in matching the speed of the arithmetical and logical unit.
In certain applications, in order to provide a check on a group of binary values (e.g. a word, byte, or character), a parity function is commonly computed by forming the modulo-2 sum of the bits in the group. The generated sum, a redundant value, is called the parity bit. The parity bit is 0 if the number of 1s in the original group was even. The parity bit is 1 if the number of 1s in the original group was odd.
The parity computation just defined will cause the augmented group of binary values (the original group plus the parity bit) to have an even number of 1s; this is called even parity. In some cases, hardware considerations make it desirable to have an odd number of 1s in the augmented group, and the parity bit is selected to cause the total number of 1s to be odd; this is called odd parity. A parity check, or odd-even-check, is the computation, or recomputation for verification, of a parity bit to determine if a prescribed parity condition is present.
Shift units in applications comprising a parity function have to restore the parity after each shifting operation since the sum of bits in a respective group might have been changed. This is generally accomplished by a parity generation subsequent to the shifting operation. As an additional security feature some applications further comprise a parity prediction function predicting the new parity bits independently from the parity generation of the shift unit. The generated and the predicted parity bits are compared and a defect in either the parity generation or prediction unit in case of a non-matching of both parity bits is apparent. However, such parity analysis require a certain amount of processing time and are consequently especially critical with respect to a demanded matching in timing with other processing units.
As shown in FIG. 1, the operand to be shifted (e.g. 4 or 8 byte) is generally read from a Data Local Store DLS and put into operand registers A REG or B REG. In a next cycle the data are processed in either one of the processing units, e.g. shifted, and written back to the Data In Register DI of the DLS. In parity checked systems a byte parity, e.g. the byte parity P0-P7, of the shifted data is generated adding additional delay to the shifter path.
Shift operations usually, e.g. in IBM S/390 based computers (IBM and S/390 are registered trademarks of International Business Machines Corporation) perform 4 or 8 byte shifts, right or left as logical or arithmetical operations. In addition a whole variety of special micro instructions are usually executed by the shift unit.

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